endpoint_number=3, # EP 3 IN
max_packet_size=usbmidi.MAX_PACKET_SIZE,
byte_width=ila.bytes_per_sample)
usbmidi.additional_endpoints.append(ila_endpoint)
m.d.comb += [
ila_endpoint.stream.stream_eq(ila.stream),
ila.trigger.eq(usb_ready & usb_valid),
]
ILACoreParameters(ila).pickle()
led = platform.request("debug_led")
m.d.comb += [
led[0].eq(usbmidi.usb_tx_active_out),
led[1].eq(usbmidi.usb_rx_active_out),
led[2].eq(usbmidi.usb_suspended_out),
led[3].eq(usbmidi.usb_reset_detected_out),
]
return m
if __name__ == "__main__":
#os.environ["LUNA_PLATFORM"] = "qmtech_xc7a35t_platform:JT51SynthPlatform"
os.environ["LUNA_PLATFORM"] = "qmtech_ep4ce15_platform:JT51SynthPlatform"
# use DE0Nano temporarily for testing until I get the USB3320 board
#os.environ["LUNA_PLATFORM"] = "de0nanoplatform:DE0NanoPlatform"
top_level_cli(JT51Synth)
endianness="big")
usb.add_endpoint(status_ep)
m.d.comb += status_ep.signal.eq(counter)
# Add a stream endpoint to our device.
iso_ep = USBIsochronousInEndpoint(endpoint_number=ISO_ENDPOINT_NUMBER,
max_packet_size=MAX_ISO_PACKET_SIZE)
usb.add_endpoint(iso_ep)
# We'll tie our address directly to our value, ensuring that we always
# count as each offset is increased.
m.d.comb += [
iso_ep.bytes_in_frame.eq(MAX_ISO_PACKET_SIZE),
iso_ep.value.eq(iso_ep.address)
]
# Connect our device as a high speed device by default.
m.d.comb += [
usb.connect.eq(1),
usb.full_speed_only.eq(1 if os.getenv('LUNA_FULL_ONLY') else 0),
]
return m
if __name__ == "__main__":
from luna import top_level_cli
device = top_level_cli(Device)
elapsed = end_time - start_time
f.close()
# Cancel all of our active transfers.
for transfer in active_transfers:
if transfer.isSubmitted():
transfer.cancel()
# If we failed out; indicate it.
if (failed_out):
logging.error(
f"Test failed because a transfer {_messages[failed_out]}.")
sys.exit(failed_out)
bytes_per_second = total_data_exchanged / elapsed
logging.info(
f"Exchanged {total_data_exchanged / 1000000}MB total at {bytes_per_second / 1000000}MB/s."
)
if __name__ == "__main__":
device = top_level_cli(USBInSpeedTestDevice)
logging.info("Giving the device time to connect...")
time.sleep(5)
if device is not None:
logging.info(f"Starting bulk in speed test.")
run_speed_test()
counter = Signal(32)
m.d.usb += counter.eq(counter + 1)
# Create our USB device interface...
ulpi = platform.request(platform.default_usb_connection)
m.submodules.usb = usb = USBDevice(bus=ulpi)
# Add our standard control endpoint to the device.
descriptors = self.create_descriptors()
usb.add_standard_control_endpoint(descriptors)
# Create an interrupt endpoint which will carry the value of our counter to the host
# each time our interrupt EP is polled.
status_ep = USBSignalInEndpoint(width=32,
endpoint_number=1,
endianness="big")
usb.add_endpoint(status_ep)
m.d.comb += status_ep.signal.eq(counter)
# Connect our device as a high speed device by default.
m.d.comb += [
usb.connect.eq(1),
usb.full_speed_only.eq(1 if os.getenv('LUNA_FULL_ONLY') else 0),
]
return m
if __name__ == "__main__":
top_level_cli(USBInterruptExample)
@named_test("Host PHY")
def test_host_phy(self, dut):
self.assertPhyPresence(REGISTER_HOST_ADDR)
@named_test("Target PHY")
def test_target_phy(self, dut):
self.assertPhyPresence(REGISTER_TARGET_ADDR)
@named_test("Sideband PHY")
def test_sideband_phy(self, dut):
self.assertPhyPresence(REGISTER_SIDEBAND_ADDR)
@named_test("HyperRAM")
def test_hyperram(self, dut):
self.assertHyperRAMRegister(0, 0x0c81)
if __name__ == "__main__":
tester = top_level_cli(InteractiveSelftest)
if tester:
tester.run_tests()
print()
# Generate our domain clocks/resets.
m.submodules.car = platform.clock_domain_generator()
# Create our USB device interface...
ulpi = platform.request("target_phy")
m.submodules.usb = usb = USBDevice(bus=ulpi)
# Add our standard control endpoint to the device.
descriptors = self.create_descriptors()
usb.add_standard_control_endpoint(descriptors)
# Connect our device as a high speed device by default.
m.d.comb += [
usb.connect.eq(1),
usb.full_speed_only.eq(1 if os.getenv('LUNA_FULL_ONLY') else 0),
]
# ... and for now, attach our LEDs to our most recent control request.
m.d.comb += [
platform.request('led', 0).eq(usb.tx_activity_led),
platform.request('led', 1).eq(usb.rx_activity_led),
platform.request('led', 2).eq(usb.suspended),
]
return m
if __name__ == "__main__":
top_level_cli(USBDeviceExample)
# Create a simple SFR that will trigger an ILA capture when written,
# and which will display our sample status read.
spi_registers.add_sfr(REGISTER_ILA,
read=self.ila.complete,
write_strobe=self.ila.trigger)
# Attach the LEDs and User I/O to the MSBs of our counter.
leds = [platform.request("led", i, dir="o") for i in range(0, 6)]
m.d.comb += Cat(leds).eq(self.counter[-7:-1])
# Return our elaborated module.
return m
if __name__ == "__main__":
example = top_level_cli(ILASharedBusExample)
# Create a debug and ILA connection.
debugger = ApolloDebugger()
ila = ApolloILAFrontend(debugger, ila=example.ila, use_inverted_cs=True)
# Trigger an ILA capture.
debugger.spi.register_write(REGISTER_ILA, 0)
# Wait for the capture to be complete.
while not debugger.spi.register_read(REGISTER_ILA):
time.sleep(0.001)
# Finally, read back the capture and display it on-screen.
ila.interactive_display()
m = Module()
# Generate our domain clocks/resets.
m.submodules.car = platform.clock_domain_generator()
# Create our USB device interface...
ulpi = platform.request("target_phy")
m.submodules.usb = usb = USBDevice(bus=ulpi)
# Add our standard control endpoint to the device.
descriptors = self.create_descriptors()
usb.add_standard_control_endpoint(descriptors)
# Add our endpoint.
test_ep = StressTestEndpoint(endpoint_number=BULK_ENDPOINT_NUMBER,
max_packet_size=MAX_BULK_PACKET_SIZE,
constant=CONSTANT_TO_SEND)
usb.add_endpoint(test_ep)
# Connect our device as a high speed device by default.
m.d.comb += [
usb.connect.eq(1),
usb.full_speed_only.eq(1 if os.getenv('LUNA_FULL_ONLY') else 0),
]
return m
if __name__ == "__main__":
top_level_cli(USBStressTest)
]
# Debug output.
m.d.comb += [
platform.request("user_io", 0, dir="o").eq(ClockSignal("usb")),
platform.request("user_io", 1, dir="o").eq(ulpi.dir),
platform.request("user_io", 2, dir="o").eq(ulpi.nxt),
platform.request("user_io", 3, dir="o").eq(analyzer.sampling),
]
# Return our elaborated module.
return m
if __name__ == "__main__":
analyzer = top_level_cli(ULPIDiagnostic)
debugger = ApolloDebugger()
time.sleep(1)
def data_is_available():
return debugger.spi.register_read(DATA_AVAILABLE)
def read_byte():
return debugger.spi.register_read(ANALYZER_RESULT)
def get_next_byte():
while not data_is_available():
time.sleep(0.1)
return read_byte()
from luna import top_level_cli
from luna.gateware.usb.devices.hid import HIDDevice
class USBHIDExample(Elaboratable):
def elaborate(self, platform):
m = Module()
# Generate our domain clocks/resets.
m.submodules.car = platform.clock_domain_generator()
# Create the 32-bit counter we'll be using as our status signal.
counter = Signal(32)
m.d.usb += counter.eq(counter + 1)
# Create our USB device interface...
ulpi = platform.request(platform.default_usb_connection)
m.submodules.hid = hid = \
HIDDevice(bus=ulpi, idVendor=0x1337, idProduct=0x1337)
# Connect counter as a pollable report
hid.add_input(counter)
m.d.comb += [hid.connect.eq(1)]
return m
if __name__ == "__main__":
top_level_cli(USBHIDExample)
m.submodules.usb = usb = USBDevice(bus=ulpi)
# Add our standard control endpoint to the device.
descriptors = self.create_descriptors()
usb.add_standard_control_endpoint(descriptors)
# Add a stream endpoint to our device.
iso_ep = USBIsochronousInEndpoint(
endpoint_number=self.ISO_ENDPOINT_NUMBER,
max_packet_size=self.MAX_ISO_PACKET_SIZE)
usb.add_endpoint(iso_ep)
# We'll tie our address directly to our value, ensuring that we always
# count as each offset is increased.
m.d.comb += [
iso_ep.bytes_in_frame.eq(self.MAX_ISO_PACKET_SIZE * 3),
iso_ep.value.eq(iso_ep.address)
]
# Connect our device as a high speed device by default.
m.d.comb += [
usb.connect.eq(1),
usb.full_speed_only.eq(1 if os.getenv('LUNA_FULL_ONLY') else 0),
]
return m
if __name__ == "__main__":
top_level_cli(USBIsochronousCounterDeviceExample)
i.bInterfaceNumber = 0
return descriptors
def elaborate(self, platform):
m = Module()
# Generate our domain clocks/resets.
m.submodules.car = platform.clock_domain_generator()
# Create our core PIPE PHY. Since PHY configuration is per-board, we'll just ask
# our platform for a pre-configured USB3 PHY.
m.submodules.phy = phy = platform.create_usb3_phy()
# Create our core SuperSpeed device.
m.submodules.usb = usb = USBSuperSpeedDevice(phy=phy)
# Add our standard control endpoint to the device.
descriptors = self.create_descriptors()
control_ep = usb.add_standard_control_endpoint(descriptors)
# Add our vendor request handler to our control endpoint.
control_ep.add_request_handler(LEDRequestHandler())
# Return our elaborated module.
return m
if __name__ == "__main__":
top_level_cli(SuperSpeedVendorDeviceExample)
# Generate our domain clocks/resets.
m.submodules.car = platform.clock_domain_generator()
# Create our core PIPE PHY. Since PHY configuration is per-board, we'll just ask
# our platform for a pre-configured USB3 PHY.
m.submodules.phy = phy = platform.create_usb3_phy()
if WITH_ILA:
# Grab the SerDes from our PHY, for debugging.
serdes = phy.serdes
m.d.comb += [
# ILA
self.serdes_rx.eq(serdes.source.data),
self.ctrl.eq(serdes.source.ctrl),
self.valid.eq(serdes.source.valid),
self.rx_gpio.eq(serdes.rx_gpio),
self.ila.trigger.eq(~serdes.rx_gpio)
]
# Return our elaborated module.
return m
if __name__ == "__main__":
ex = top_level_cli(PIPEPhyExample)
if WITH_ILA:
ex.emit()
m.d.comb += [
ram_bus.reset.eq(0),
psram.single_page.eq(0),
psram.perform_write.eq(0),
psram.register_space.eq(1),
psram.final_word.eq(1),
psram.start_transfer.eq(psram_address_changed),
psram.address.eq(psram_address),
]
# Return our elaborated module.
return m
if __name__ == "__main__":
test = top_level_cli(HyperRAMDiagnostic)
# Create a debug and ILA connection.
dut = ApolloDebugger()
logging.info(
f"Connected to onboard dut; hardware revision r{dut.major}.{dut.minor} (s/n: {dut.serial_number})."
)
logging.info("Running basic HyperRAM diagnostics.")
iterations = 100
passes = 0
failures = 0
failed_tests = set()
platform.request("pass_through_vbus").eq(1),
]
# Hook up our LEDs to status signals.
m.d.comb += [
platform.request("led", 0).eq(umti.vbus_valid),
platform.request("led", 1).eq(umti.session_valid),
platform.request("led", 2).eq(umti.session_end),
platform.request("led", 3).eq(umti.rx_active),
platform.request("led", 4).eq(umti.rx_error)
]
spi_registers.add_read_only_register(1, read=umti.last_rx_command)
# For debugging: mirror some ULPI signals on the UIO.
user_io = Cat(
platform.request("user_io", i, dir="o") for i in range(0, 4))
m.d.comb += [
user_io[0].eq(ClockSignal("ulpi")),
user_io[1].eq(ulpi.dir),
user_io[2].eq(ulpi.nxt),
user_io[3].eq(ulpi.stp),
]
# Return our elaborated module.
return m
if __name__ == "__main__":
top_level_cli(ULPIDiagnostic)
letters = Array(ord(i) for i in "Hello, world! \r\n")
# ... and count through it whenever we send a letter.
current_letter = Signal(range(0, len(letters)))
with m.If(stream.ready):
m.d.sync += current_letter.eq(current_letter + 1)
# Hook everything up.
m.d.comb += [
stream.payload .eq(letters[current_letter]),
stream.valid .eq(counter == 0),
uart.tx.o .eq(transmitter.tx),
]
# If this platform has an output-enable control on its UART, drive it iff
# we're actively driving a transmission.
if hasattr(uart.tx, 'oe'):
m.d.comb += uart.tx.oe.eq(transmitter.driving),
# Turn on a single LED, just to show something's running.
led = Cat(platform.request('led', i) for i in range(6))
m.d.comb += led.eq(~transmitter.tx)
return m
if __name__ == "__main__":
top_level_cli(UARTBridgeExample)
class USBSerialDeviceExample(Elaboratable):
""" Device that acts as a 'USB-to-serial' loopback using our premade gateware. """
def elaborate(self, platform):
m = Module()
# Generate our domain clocks/resets.
m.submodules.car = platform.clock_domain_generator()
# Create our USB-to-serial converter.
ulpi = platform.request(platform.default_usb_connection)
m.submodules.usb_serial = usb_serial = \
USBSerialDevice(bus=ulpi, idVendor=0x16d0, idProduct=0x0f3b)
m.d.comb += [
# Place the streams into a loopback configuration...
usb_serial.tx.payload .eq(usb_serial.rx.payload),
usb_serial.tx.valid .eq(usb_serial.rx.valid),
usb_serial.tx.first .eq(usb_serial.rx.first),
usb_serial.tx.last .eq(usb_serial.rx.last),
usb_serial.rx.ready .eq(usb_serial.tx.ready),
# ... and always connect by default.
usb_serial.connect .eq(1)
]
return m
if __name__ == "__main__":
top_level_cli(USBSerialDeviceExample)
# Heartbeat LED.
counter = Signal(28)
m.d.ss += counter.eq(counter + 1)
m.d.comb += [
platform.get_led(m, 0).o.eq(usb.link_trained),
# Heartbeat.
platform.get_led(m, 7).o.eq(counter[-1])
]
if WITH_ILA:
m.d.comb += [
# ILA
self.ila_data .eq(usb.rx_data_tap.data),
self.ila_ctrl .eq(usb.rx_data_tap.ctrl),
self.ila_valid .eq(usb.rx_data_tap.valid),
self.ila.trigger .eq(usb.link_trained)
]
# Return our elaborated module.
return m
if __name__ == "__main__":
ex = top_level_cli(USBSuperSpeedExample)
if WITH_ILA:
ex.emit()
""" Gateware meant to demonstrate use of the Debug Controller's register interface. """
def elaborate(self, platform):
m = Module()
board_spi = platform.request("debug_spi")
# Create a set of registers, and expose them over SPI.
spi_registers = SPIRegisterInterface(
default_read_value=0x4C554E41) #default read = u'LUNA'
m.submodules.spi_registers = spi_registers
# Fill in some example registers.
# (Register 0 is reserved for size autonegotiation).
spi_registers.add_read_only_register(1, read=0xc001cafe)
led_reg = spi_registers.add_register(2, size=6, name="leds")
spi_registers.add_read_only_register(3, read=0xdeadbeef)
# ... and tie our LED register to our LEDs.
led_out = Cat(
[platform.request("led", i, dir="o") for i in range(0, 6)])
m.d.comb += led_out.eq(led_reg)
# Connect up our synchronized copies of the SPI registers.
spi = synchronize(m, board_spi)
m.d.comb += spi_registers.spi.connect(spi)
return m
if __name__ == "__main__":
top_level_cli(DebugSPIRegisterExample)
""" Hardware module that validates basic LUNA functionality. """
def elaborate(self, platform):
""" Generate the Blinky tester. """
m = Module()
# Grab our I/O connectors.
leds = [
platform.request_optional("led", i, default=NullPin()).o
for i in range(0, 8)
]
user_io = [
platform.request_optional("user_io", i, default=NullPin()).o
for i in range(0, 8)
]
# Clock divider / counter.
counter = Signal(28)
m.d.sync += counter.eq(counter + 1)
# Attach the LEDs and User I/O to the MSBs of our counter.
m.d.comb += Cat(leds).eq(counter[-7:-1])
m.d.comb += Cat(user_io).eq(counter[7:21])
# Return our elaborated module.
return m
if __name__ == "__main__":
top_level_cli(Blinky)
def __init__(self):
# Base ourselves around an SPI command interface.
self.interface = SPIDeviceInterface(clock_phase=1)
def elaborate(self, platform):
m = Module()
board_spi = platform.request("debug_spi")
# Use our command interface.
m.submodules.interface = self.interface
#
# Synchronize and connect our SPI.
#
spi = synchronize(m, board_spi)
m.d.comb += self.interface.spi.connect(spi)
# Turn on a single LED, just to show something's running.
led = platform.request('led', 0)
m.d.comb += led.eq(1)
# Echo back the last received data.
m.d.comb += self.interface.word_out.eq(self.interface.word_in)
return m
if __name__ == "__main__":
top_level_cli(DebugSPIExample)
max_packet_size=self.MAX_BULK_PACKET_SIZE
)
usb.add_endpoint(stream_ep)
leds = Cat(platform.request("led", i) for i in range(6))
user_io = Cat(platform.request("user_io", i, dir="o") for i in range(4))
# Always stream our USB data directly onto our User I/O and LEDS.
with m.If(stream_ep.stream.valid):
m.d.usb += [
leds .eq(stream_ep.stream.payload),
user_io .eq(stream_ep.stream.payload),
]
# Always accept data as it comes in.
m.d.comb += stream_ep.stream.ready.eq(1)
# Connect our device as a high speed device by default.
m.d.comb += [
usb.connect .eq(1),
usb.full_speed_only .eq(1 if os.getenv('LUNA_FULL_ONLY') else 0),
]
return m
if __name__ == "__main__":
top_level_cli(USBStreamOutDeviceExample)
stream_ep = USBStreamInEndpoint(
endpoint_number=self.BULK_ENDPOINT_NUMBER,
max_packet_size=self.MAX_BULK_PACKET_SIZE
)
usb.add_endpoint(stream_ep)
# Always generate a monotonic count for our stream, which counts every time our
# stream endpoint accepts a data byte.
counter = Signal(8)
with m.If(stream_ep.stream.ready):
m.d.usb += counter.eq(counter + 1)
m.d.comb += [
stream_ep.stream.valid .eq(1),
stream_ep.stream.payload .eq(counter)
]
# Connect our device as a high speed device by default.
m.d.comb += [
usb.connect .eq(1),
usb.full_speed_only .eq(1 if os.getenv('LUNA_FULL_ONLY') else 0),
]
return m
if __name__ == "__main__":
top_level_cli(USBCounterDeviceExample)
def elaborate(self, platform):
m = Module()
m.submodules += self.ila
# Generate our domain clocks/resets.
m.submodules.car = platform.clock_domain_generator()
# Clock divider / counter.
m.d.usb += self.counter.eq(self.counter + 1)
# Say "hello world" constantly over our ILA...
letters = Array(ord(i) for i in "Hello, world! \r\n")
current_letter = Signal(range(0, len(letters)))
m.d.sync += current_letter.eq(current_letter + 1)
m.d.comb += self.hello.eq(letters[current_letter])
# Set our ILA to trigger each time the counter is at a random value.
# This shows off our example a bit better than counting at zero.
m.d.comb += self.ila.trigger.eq(self.counter == 227)
# Return our elaborated module.
return m
if __name__ == "__main__":
example = top_level_cli(ILAExample)
example.interactive_display()
return descriptors
def elaborate(self, platform):
m = Module()
# Generate our domain clocks/resets.
m.submodules.car = platform.clock_domain_generator()
# Create our USB device interface...
ulpi = platform.request("target_phy")
m.submodules.usb = usb = USBDevice(bus=ulpi)
# Add our standard control endpoint to the device.
descriptors = self.create_descriptors()
control_ep = usb.add_standard_control_endpoint(descriptors)
# Add our custom request handlers.
control_ep.add_request_handler(LEDRequestHandler())
# Connect our device by default.
m.d.comb += usb.connect.eq(1)
return m
if __name__ == "__main__":
top_level_cli(USBVendorDeviceExample)
for peripheral in peripherals:
soc.add_peripheral(peripheral)
def elaborate(self, platform):
m = Module()
m.submodules.car = platform.clock_domain_generator(
clock_frequencies=CLOCK_FREQUENCIES_MHZ)
# Add our SoC to the design...
m.submodules.soc = self.soc
# ... and connect up its UART.
uart_io = platform.request("uart", 0)
m.d.comb += [
uart_io.tx.eq(self.uart.tx),
self.uart.rx.eq(uart_io.rx),
]
if hasattr(uart_io.tx, 'oe'):
m.d.comb += uart_io.tx.oe.eq(self.uart.driving
& self.uart.enabled),
return m
if __name__ == "__main__":
design = SelftestCore()
top_level_cli(design, cli_soc=design.soc)
from luna import top_level_cli
from luna.gateware.soc import SimpleSoC
from luna.gateware.interface.uart import UARTTransmitterPeripheral
class LunaCPUExample(Elaboratable):
""" Simple example of building a simple SoC around LUNA. """
def elaborate(self, platform):
m = Module()
clock_freq = 60e6
# Grab a reference to our UART.
uart_io = platform.request("uart", 0)
# Create our SoC...
m.submodules.soc = soc = SimpleSoC()
soc.add_firmware_rom('hello_world.bin')
# ... and add our UART peripheral.
uart = UARTTransmitterPeripheral(divisor=int(clock_freq // 115200))
soc.add_peripheral(uart, addr=0x80000000, sparse=True)
# Connect the transmitter to the debug transmitter output.
m.d.comb += uart_io.tx.o.eq(uart.tx)
return m
if __name__ == "__main__":
top_level_cli(LunaCPUExample)
