Ejemplo n.º 1
0
class X86GPUTLB(ClockedObject):
    type = 'X86GPUTLB'
    cxx_class = 'gem5::X86ISA::GpuTLB'
    cxx_header = 'gpu-compute/gpu_tlb.hh'
    size = Param.Int(64, "TLB size (number of entries)")
    assoc = Param.Int(64, "TLB associativity")

    if buildEnv.get('FULL_SYSTEM', False):
        walker = Param.X86PagetableWalker(X86PagetableWalker(),
                                          "page table walker")

    hitLatency = Param.Int(2, "Latency of a TLB hit")
    missLatency1 = Param.Int(5, "Latency #1 of a TLB miss")
    missLatency2 = Param.Int(100, "Latency #2 of a TLB miss")
    maxOutstandingReqs = Param.Int(64, "# of maximum outstanding requests")
    cpu_side_ports = VectorResponsePort("Ports on side closer to CPU/CU")
    slave = DeprecatedParam(cpu_side_ports,
                            '`slave` is now called `cpu_side_ports`')
    mem_side_ports = VectorRequestPort("Ports on side closer to memory")
    master = DeprecatedParam(mem_side_ports,
                             '`master` is now called `mem_side_ports`')
    allocationPolicy = Param.Bool(True, "Allocate on an access")
    accessDistance = Param.Bool(False, "print accessDistance stats")
Ejemplo n.º 2
0
# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.

from m5.defines import buildEnv
from m5.params import *
from m5.proxy import *

from m5.objects.ClockedObject import ClockedObject
from m5.SimObject import SimObject

if buildEnv.get('FULL_SYSTEM', False):

    class X86PagetableWalker(SimObject):
        type = 'X86PagetableWalker'
        cxx_class = 'gem5::X86ISA::Walker'
        port = ResponsePort("Port for the hardware table walker")
        system = Param.System(Parent.any, "system object")


class X86GPUTLB(ClockedObject):
    type = 'X86GPUTLB'
    cxx_class = 'gem5::X86ISA::GpuTLB'
    cxx_header = 'gpu-compute/gpu_tlb.hh'
    size = Param.Int(64, "TLB size (number of entries)")
    assoc = Param.Int(64, "TLB associativity")