Ejemplo n.º 1
0
def gen_model(real_type):
    # declare module
    m = MixedSignalModel('model', real_type=real_type)
    m.add_analog_input('a')
    m.add_analog_input('b')
    m.add_digital_output('c')

    # bind expression to internal signal
    m.set_this_cycle(m.c, m.a > m.b)

    # compile to a file
    BUILD_DIR.mkdir(parents=True, exist_ok=True)
    model_file = BUILD_DIR / 'model.sv'
    m.compile_to_file(VerilogGenerator(), filename=model_file)

    # return file location
    return model_file
Ejemplo n.º 2
0
def gen_model():
    # declare model I/O
    m = MixedSignalModel('model')
    m.add_digital_input('a', width=63, signed=True)
    m.add_digital_input('b', width=63, signed=True)
    m.add_digital_output('c', width=64, signed=True)

    # assign expression to output
    m.bind_name('d', m.a - m.b)
    m.set_this_cycle(m.c, m.d)

    # compile to a file
    BUILD_DIR.mkdir(parents=True, exist_ok=True)
    model_file = BUILD_DIR / 'model.sv'
    m.compile_to_file(VerilogGenerator(), filename=model_file)

    # return file location
    return model_file
Ejemplo n.º 3
0
def gen_model():
    # declare module
    m = MixedSignalModel('model')
    m.add_digital_input('clk')
    m.add_digital_input('rst')
    m.add_digital_input('seed', width=32)
    m.add_digital_output('out', width=32)

    # sum signals to output
    m.set_this_cycle(m.out, mt19937(clk=m.clk, rst=m.rst, seed=m.seed))

    # compile to a file
    BUILD_DIR.mkdir(parents=True, exist_ok=True)
    model_file = BUILD_DIR / 'model.sv'
    m.compile_to_file(VerilogGenerator(), filename=model_file)

    # return file location
    return model_file
Ejemplo n.º 4
0
def gen_model(width, init, real_type):
    # declare module
    m = MixedSignalModel('model', real_type=real_type)
    m.add_digital_input('clk')
    m.add_digital_input('rst')
    m.add_digital_output('out', width=width)

    # bind expression to internal signal
    lfsr = m.lfsr_signal(width, clk=m.clk, rst=m.rst, init=init)
    m.set_this_cycle(m.out, lfsr)

    # compile to a file
    BUILD_DIR.mkdir(parents=True, exist_ok=True)
    model_file = BUILD_DIR / 'model.sv'
    m.compile_to_file(VerilogGenerator(), filename=model_file)

    # return file location
    return model_file
Ejemplo n.º 5
0
def gen_model(n, vn, vp, dt, real_type):
    # declare model I/O
    m = MixedSignalModel('model', dt=dt, real_type=real_type)
    m.add_analog_input('a_in')
    m.add_digital_output('d_out', width=n, signed=True)

    # compute expression for ADC output as an unclamped, real number
    expr = ((m.a_in - vn) / (vp - vn) * ((2**n) - 1)) - (2**(n - 1))

    # clamp to ADC range
    clamped = clamp_op(expr, -(2**(n - 1)), (2**(n - 1)) - 1)

    # assign expression to output
    m.set_this_cycle(m.d_out, to_sint(clamped, width=n))

    # compile to a file
    BUILD_DIR.mkdir(parents=True, exist_ok=True)
    model_file = BUILD_DIR / 'model.sv'
    m.compile_to_file(VerilogGenerator(), filename=model_file)

    # return file location
    return model_file