class Foo(m.Circuit):
io = m.IO(a=m.In(m.Bits[8]),
b=m.In(m.Bits[8]),
c=m.In(m.Bits[8]),
x=m.Out(m.Bits[8]),
y=m.Out(m.Bits[8]))
io += m.ClockIO(has_resetn=True)
x = [m.bits(0, 8), m.bits(0, 8), m.bits(1, 8), m.bits(0, 8)]
if should_pass:
y = [m.bits(0, 8), m.bits(1, 8), m.bits(2, 8), m.bits(3, 8)]
else:
y = [m.bits(1, 8), m.bits(1, 8), m.bits(1, 8), m.bits(1, 8)]
count = m.Register(m.Bits[2])()
count.I @= count.O + 1
io.x @= m.mux(x, count.O)
io.y @= m.mux(y, count.O)
m.display("io.x=%x, io.y=%x", io.x, io.y).when(m.posedge(io.CLK))
if use_sva:
f.assert_(f.sva(f.not_(f.onehot(io.a)), "&&", io.b.reduce_or(),
"&&", io.x[0].value(), "|=>",
io.y.value() != f.past(io.y.value(), 2)),
name="name_A",
on=f.posedge(io.CLK),
disable_iff=f.not_(io.RESETN))
else:
f.assert_(
# Note parens matter!
(f.not_(f.onehot(io.a)) & io.b.reduce_or() & io.x[0].value())
| f.implies | f.delay[1] | (io.y != f.past(io.y.value(), 2)),
name="name_A",
on=f.posedge(io.CLK),
disable_iff=f.not_(io.RESETN))
class DUT(m.Circuit):
io = m.IO(done=m.Out(m.Bit)) + m.ClockIO(has_reset=True)
core = Core(
x_len, data_path_kwargs=m.generator.ParamDict(ImmGen=ImmGen))()
core.host.fromhost.data.undriven()
core.host.fromhost.valid @= False
# reverse concat because we're using utils with chisel ordering
_hex = [concat(*reversed(x)) for x in loadmem]
imem = RegFileBuilder("imem",
1 << 20,
x_len,
write_forward=False,
reset_type=m.Reset,
backend="verilog")
dmem = RegFileBuilder("dmem",
1 << 20,
x_len,
write_forward=False,
reset_type=m.Reset,
backend="verilog")
INIT, RUN = False, True
state = m.Register(init=INIT)()
cycle = m.Register(m.UInt[32])()
n = len(_hex)
counter = CounterModM(n, n.bit_length(), has_ce=True)
counter.CE @= m.enable(state.O == INIT)
cntr, done = counter.O, counter.COUT
iaddr = (core.icache.req.data.addr // (x_len // 8))[:20]
daddr = (core.dcache.req.data.addr // (x_len // 8))[:20]
dmem_data = dmem[daddr]
imem_data = imem[iaddr]
write = 0
for i in range(x_len // 8):
write |= m.zext_to(
m.mux([dmem_data, core.dcache.req.data.data],
core.dcache.req.valid
& core.dcache.req.data.mask[i])[8 * i:8 * (i + 1)],
32) << (8 * i)
core.RESET @= m.reset(state.O == INIT)
core.icache.resp.valid @= state.O == RUN
core.dcache.resp.valid @= state.O == RUN
core.icache.resp.data.data @= m.Register(
m.UInt[x_len])()(imem_data)
core.dcache.resp.data.data @= m.Register(
m.UInt[x_len])()(dmem_data)
chunk = m.mux(_hex, cntr)
imem.write(m.zext_to(cntr, 20), chunk, m.enable(state.O == INIT))
dmem.write(
m.mux([m.zext_to(cntr, 20), daddr], state.O == INIT),
m.mux([chunk, write], state.O == INIT),
m.enable((state.O == INIT)
| (core.dcache.req.valid
& core.dcache.req.data.mask.reduce_or())))
@m.inline_combinational()
def logic():
state.I @= state.O
cycle.I @= cycle.O
if state.O == INIT:
if done:
state.I @= RUN
if state.O == RUN:
cycle.I @= cycle.O + 1
debug = False
if debug:
m.display("LOADMEM[%x] <= %x", cntr * (x_len // 8),
chunk).when(m.posedge(io.CLK)).if_(state.O == INIT)
m.display("INST[%x] => %x",
iaddr * (x_len // 8), dmem_data).when(
m.posedge(io.CLK)).if_((state.O == RUN)
& core.icache.req.valid)
m.display("MEM[%x] <= %x", daddr * (x_len // 8), write).when(
m.posedge(
io.CLK)).if_((state.O == RUN) & core.dcache.req.valid
& core.dcache.req.data.mask.reduce_or())
m.display(
"MEM[%x] => %x", daddr * (x_len // 8),
dmem_data).when(m.posedge(
io.CLK)).if_((state.O == RUN) & core.dcache.req.valid
& ~core.dcache.req.data.mask.reduce_or())
m.display("cycles: %d", cycle.O).when(m.posedge(
io.CLK)).if_(io.done.value() == 1)
f.assert_immediate(cycle.O < test.maxcycles)
io.done @= core.host.tohost != 0
f.assert_immediate(
(core.host.tohost >> 1) == 0,
failure_msg=("* tohost: %d *", core.host.tohost))
class DUT(m.Circuit):
io = m.IO(done=m.Out(m.Bit)) + m.ClockIO()
x_len = 32
n_sets = 256
b_bytes = 4 * (x_len >> 3)
b_len = m.bitutils.clog2(b_bytes)
s_len = m.bitutils.clog2(n_sets)
t_len = x_len - (s_len + b_len)
nasti_params = NastiParameters(data_bits=64,
addr_bits=x_len,
id_bits=5)
dut = Cache(x_len, 1, n_sets, b_bytes)()
dut_mem = make_NastiIO(nasti_params).undirected_t(name="dut_mem")
dut_mem.ar @= make_Queue(dut.nasti.ar, 32)
dut_mem.aw @= make_Queue(dut.nasti.aw, 32)
dut_mem.w @= make_Queue(dut.nasti.w, 32)
dut.nasti.b @= make_Queue(dut_mem.b, 32)
dut.nasti.r @= make_Queue(dut_mem.r, 32)
gold = GoldCache(x_len, 1, n_sets, b_bytes)()
gold_req = type(gold.req).undirected_t(name="gold_req")
gold_resp = type(gold.resp).undirected_t(name="gold_resp")
gold_mem = make_NastiIO(nasti_params).undirected_t(name="gold_mem")
gold.req @= make_Queue(gold_req, 32)
gold_resp @= make_Queue(gold.resp, 32)
gold_mem.ar @= make_Queue(gold.nasti.ar, 32)
gold_mem.aw @= make_Queue(gold.nasti.aw, 32)
gold_mem.w @= make_Queue(gold.nasti.w, 32)
gold.nasti.b @= make_Queue(gold_mem.b, 32)
gold.nasti.r @= make_Queue(gold_mem.r, 32)
size = m.bitutils.clog2(nasti_params.x_data_bits // 8)
b_bits = b_bytes << 3
data_beats = b_bits // nasti_params.x_data_bits
mem = m.Memory(1 << 20, m.UInt[nasti_params.x_data_bits])()
class MemState(m.Enum):
IDLE = 0
WRITE = 1
WRITE_ACK = 2
READ = 3
mem_state = m.Register(init=MemState.IDLE)()
write_counter = mantle.CounterModM(data_beats,
data_beats.bit_length(),
has_ce=True)
write_counter.CE @= m.enable((mem_state.O == MemState.WRITE)
& dut_mem.w.valid & gold_mem.w.valid)
read_counter = mantle.CounterModM(data_beats,
data_beats.bit_length(),
has_ce=True)
read_counter.CE @= m.enable((mem_state.O == MemState.READ)
& dut_mem.r.ready & gold_mem.r.ready)
dut_mem.b.valid @= mem_state.O == MemState.WRITE_ACK
dut_mem.b.data @= NastiWriteResponseChannel(nasti_params, 0)
dut_mem.r.valid @= mem_state.O == MemState.READ
dut_mem.r.data @= NastiReadDataChannel(
nasti_params, 0,
mem.read(
((gold_mem.ar.data.addr) +
m.zext_to(read_counter.O, nasti_params.x_addr_bits))[:20]),
read_counter.COUT)
gold_mem.ar.ready @= dut_mem.ar.ready
gold_mem.aw.ready @= dut_mem.aw.ready
gold_mem.w.ready @= dut_mem.w.ready
gold_mem.b.valid @= dut_mem.b.valid
gold_mem.b.data @= dut_mem.b.data
gold_mem.r.valid @= dut_mem.r.valid
gold_mem.r.data @= dut_mem.r.data
mem_wen0 = m.Bit(name="mem_wen0")
mem_wdata0 = m.UInt[nasti_params.x_data_bits](name="mem_wdata0")
mem_wen1 = m.Bit(name="mem_wen1")
mem_wdata1 = m.UInt[nasti_params.x_data_bits](name="mem_wdata1")
mem_waddr1 = m.UInt[20](name="mem_waddr1")
mem.write(
m.mux([dut_mem.w.data.data, mem_wdata1], mem_wen1),
m.mux([((dut_mem.aw.data.addr) +
m.zext_to(write_counter.O, nasti_params.x_addr_bits))[:20],
mem_waddr1], mem_wen1), m.enable(mem_wen0 | mem_wen1))
# m.display("mem_wen0 = %x, mem_wen1 = %x", mem_wen0,
# mem_wen1).when(m.posedge(io.CLK))
# m.display("dut_mem.w.valid = %x",
# dut_mem.w.valid).when(m.posedge(io.CLK))
# m.display("gold_mem.w.valid = %x",
# gold_mem.w.valid).when(m.posedge(io.CLK))
f.assert_immediate(
(mem_state.O != MemState.IDLE)
| ~(gold_mem.aw.valid & dut_mem.aw.valid) |
(dut_mem.aw.data.addr == gold_mem.aw.data.addr),
failure_msg=(
"[dut_mem.aw.data.addr] %x != [gold_mem.aw.data.addr] %x",
dut_mem.aw.data.addr, gold_mem.aw.data.addr))
f.assert_immediate(
(mem_state.O != MemState.IDLE)
| ~(gold_mem.aw.valid & dut_mem.aw.valid)
| ~(gold_mem.ar.valid & dut_mem.ar.valid) |
(dut_mem.ar.data.addr == gold_mem.ar.data.addr),
failure_msg=(
"[dut_mem.ar.data.addr] %x != [gold_mem.ar.data.addr] %x",
dut_mem.ar.data.addr, gold_mem.ar.data.addr))
f.assert_immediate(
(mem_state.O != MemState.WRITE)
| ~(gold_mem.w.valid & dut_mem.w.valid) |
(dut_mem.w.data.data == gold_mem.w.data.data),
failure_msg=(
"[dut_mem.w.data.data] %x != [gold_mem.w.data.data] %x",
dut_mem.w.data.data, gold_mem.w.data.data))
@m.inline_combinational()
def mem_fsm():
dut_mem.w.ready @= False
dut_mem.aw.ready @= False
dut_mem.ar.ready @= False
mem_wen0 @= False
mem_state.I @= mem_state.O
if mem_state.O == MemState.IDLE:
if gold_mem.aw.valid & dut_mem.aw.valid:
mem_state.I @= MemState.WRITE
elif gold_mem.ar.valid & dut_mem.ar.valid:
mem_state.I @= MemState.READ
elif mem_state.O == MemState.WRITE:
if gold_mem.w.valid & dut_mem.w.valid:
mem_wen0 @= True
dut_mem.w.ready @= True
if write_counter.COUT:
dut_mem.aw.ready @= True
mem_state.I @= MemState.WRITE_ACK
elif mem_state.O == MemState.WRITE_ACK:
if gold_mem.b.ready & dut_mem.b.ready:
mem_state.I @= MemState.IDLE
elif mem_state.O == MemState.READ:
if read_counter.COUT:
dut_mem.ar.ready @= True
mem_state.I @= MemState.IDLE
if TRACE:
m.display("[%0t]: [write] mem[%x] <= %x", m.time(),
mem.WADDR.value(), dut_mem.w.data.data).when(
m.posedge(io.CLK)).if_(mem_wen0)
m.display("[%0t]: [read] mem[%x] => %x", m.time(),
mem.RADDR.value(),
dut_mem.r.data.data).when(m.posedge(
io.CLK)).if_((mem_state.O == MemState.READ)
& dut_mem.r.ready & gold_mem.r.ready)
def rand_data(nasti_params):
rand_data = BitVector[nasti_params.x_data_bits](0)
for i in range(nasti_params.x_data_bits // 8):
rand_data |= BitVector[nasti_params.x_data_bits](
random.randint(0, 0xff) << (8 * i))
return rand_data
def rand_mask(x_len):
return BitVector[x_len // 8](random.randint(
1, (1 << (x_len // 8)) - 2))
def make_test(rand_data, nasti_params, x_len):
# Wrapper because function definition in side class namespace
# doesn't inherit class variables
def test(b_bits, tag, idx, off, mask=BitVector[x_len // 8](0)):
test_data = rand_data(nasti_params)
for i in range((b_bits // nasti_params.x_data_bits) - 1):
test_data = test_data.concat(rand_data(nasti_params))
return m.uint(m.concat(off, idx, tag, test_data, mask))
return test
test = make_test(rand_data, nasti_params, x_len)
tags = []
for _ in range(3):
tags.append(BitVector.random(t_len))
idxs = []
for _ in range(2):
idxs.append(BitVector.random(s_len))
offs = []
for _ in range(6):
offs.append(BitVector.random(b_len) & -4)
init_addr = []
init_data = []
_iter = itertools.product(tags, idxs, range(0, data_beats))
for tag, idx, off in _iter:
init_addr.append(m.uint(m.concat(BitVector[b_len](off), idx, tag)))
init_data.append(rand_data(nasti_params))
test_vec = [
test(b_bits, tags[0], idxs[0], offs[0]), # 0: read miss
test(b_bits, tags[0], idxs[0], offs[1]), # 1: read hit
test(b_bits, tags[1], idxs[0], offs[0]), # 2: read miss
test(b_bits, tags[1], idxs[0], offs[2]), # 3: read hit
test(b_bits, tags[1], idxs[0], offs[3]), # 4: read hit
test(b_bits, tags[1], idxs[0], offs[4],
rand_mask(x_len)), # 5: write hit # noqa
test(b_bits, tags[1], idxs[0], offs[4]), # 6: read hit
test(b_bits, tags[2], idxs[0],
offs[5]), # 7: read miss & write back # noqa
test(b_bits, tags[0], idxs[1], offs[0],
rand_mask(x_len)), # 8: write miss # noqa
test(b_bits, tags[0], idxs[1], offs[0]), # 9: read hit
test(b_bits, tags[0], idxs[1], offs[1]), # 10: read hit
test(b_bits, tags[1], idxs[1], offs[2],
rand_mask(x_len)), # 11: write miss & write back # noqa
test(b_bits, tags[1], idxs[1], offs[3]), # 12: read hit
test(b_bits, tags[2], idxs[1], offs[4]), # 13: read write back
test(b_bits, tags[2], idxs[1], offs[5]) # 14: read hit
]
class TestState(m.Enum):
INIT = 0
START = 1
WAIT = 2
DONE = 3
state = m.Register(init=TestState.INIT)()
timeout = m.Register(m.UInt[32])()
init_m = len(init_addr) - 1
init_counter = mantle.CounterModM(init_m,
init_m.bit_length(),
has_ce=True)
init_counter.CE @= m.enable(state.O == TestState.INIT)
test_m = len(test_vec) - 1
test_counter = mantle.CounterModM(test_m,
test_m.bit_length(),
has_ce=True)
test_counter.CE @= m.enable(state.O == TestState.DONE)
curr_vec = m.mux(test_vec, test_counter.O)
mask = (curr_vec >> (b_len + s_len + t_len + b_bits))[:x_len // 8]
data = (curr_vec >> (b_len + s_len + t_len))[:b_bits]
tag = (curr_vec >> (b_len + s_len))[:t_len]
idx = (curr_vec >> b_len)[:s_len]
off = curr_vec[:b_len]
dut.cpu.req.data.addr @= m.concat(off, idx, tag)
# TODO: Is truncating this fine?
req_data = data[:x_len]
dut.cpu.req.data.data @= req_data
dut.cpu.req.data.mask @= mask
dut.cpu.req.valid @= state.O == TestState.WAIT
dut.cpu.abort @= 0
gold_req.data @= dut.cpu.req.data.value()
gold_req.valid @= state.O == TestState.START
gold_resp.ready @= state.O == TestState.DONE
mem_waddr1 @= m.mux(init_addr, init_counter.O)[:20]
mem_wdata1 @= m.mux(init_data, init_counter.O)
check_resp_data = m.Bit()
if TRACE:
m.display("[%0t]: [init] mem[%x] <= %x", m.time(),
mem_waddr1, mem_wdata1)\
.when(m.posedge(io.CLK))\
.if_(state.O == TestState.INIT)
@m.inline_combinational()
def state_fsm():
timeout.I @= timeout.O
mem_wen1 @= m.bit(False)
check_resp_data @= m.bit(False)
state.I @= state.O
if state.O == TestState.INIT:
mem_wen1 @= m.bit(True)
if init_counter.COUT:
state.I @= TestState.START
elif state.O == TestState.START:
if gold_req.ready:
timeout.I @= m.bits(0, 32)
state.I @= TestState.WAIT
elif state.O == TestState.WAIT:
timeout.I @= timeout.O + 1
if dut.cpu.resp.valid & gold_resp.valid:
if ~mask.reduce_or():
check_resp_data @= m.bit(True)
state.I @= TestState.DONE
elif state.O == TestState.DONE:
state.I @= TestState.START
f.assert_immediate((state.O != TestState.WAIT) | (timeout.O < 100))
f.assert_immediate(
~check_resp_data | (dut.cpu.resp.data.data == gold_resp.data.data),
failure_msg=("dut.cpu.resp.data.data => %x != %x",
dut.cpu.resp.data.data, gold_resp.data.data))
# m.display("mem_state=%x", mem_state.O).when(m.posedge(io.CLK))
# m.display("test_state=%x", state.O).when(m.posedge(io.CLK))
# m.display("dut req valid = %x",
# dut.cpu.req.valid).when(m.posedge(io.CLK))
# m.display("gold req valid = %x, ready = %x", gold_req.valid,
# gold_req.ready).when(m.posedge(io.CLK))
# m.display("[%0t]: dut resp data = %x, gold resp data = %x", m.time(),
# dut.cpu.resp.data.data, gold_resp.data.data)\
# .when(m.posedge(io.CLK))
io.done @= test_counter.COUT
def __init__(self, x_len, n_ways: int, n_sets: int, b_bytes: int):
nasti_params = NastiParameters(data_bits=64,
addr_bits=x_len,
id_bits=5)
self.io = m.IO(req=m.Consumer(m.Decoupled[make_CacheReq(x_len)]),
resp=m.Producer(m.Decoupled[make_CacheResp(x_len)]),
nasti=make_NastiIO(nasti_params)) + m.ClockIO()
size = m.bitutils.clog2(nasti_params.x_data_bits)
b_bits = b_bytes << 3
b_len = m.bitutils.clog2(b_bytes)
s_len = m.bitutils.clog2(n_sets)
t_len = x_len - (s_len + b_len)
nasti_params = NastiParameters(data_bits=64,
addr_bits=x_len,
id_bits=5)
data_beats = b_bits // nasti_params.x_data_bits
length = data_beats - 1
data = m.Memory(n_sets, m.UInt[b_bits])()
tags = m.Memory(n_sets, m.UInt[t_len])()
v = m.Memory(n_sets, m.Bit)()
d = m.Memory(n_sets, m.Bit)()
req = self.io.req.data
tag = (req.addr >> (b_len + s_len))[:t_len]
idx = req.addr[b_len:b_len + s_len]
off = req.addr[:b_len]
read = data.read(idx)
write = m.bits(0, b_bits)
for i in range(b_bytes):
write |= m.mux([(read & (0xff << (8 * i))),
((m.zext_to(req.data, b_bits) >>
((8 * (i & 0x3)))) & 0xff) << (8 * i)],
((off // 4) == (i // 4)) & (req.mask >>
(i & 0x3))[0])[:b_bits]
class State(m.Enum):
IDLE = 0
WRITE = 1
WRITE_ACK = 2
READ = 3
state = m.Register(init=State.IDLE)()
write_counter = mantle.CounterModM(data_beats,
max(data_beats.bit_length(), 1),
has_ce=True)
write_counter.CE @= m.enable(state.O == State.WRITE)
w_cnt, w_done = write_counter.O, write_counter.COUT
read_counter = mantle.CounterModM(data_beats,
max(data_beats.bit_length(), 1),
has_ce=True)
read_counter.CE @= m.enable((state.O == State.READ)
& self.io.nasti.r.valid)
r_cnt, r_done = read_counter.O, read_counter.COUT
self.io.resp.data.data @= (read >> (m.zext_to(
(off // 4), b_bits) * x_len))[:x_len]
self.io.nasti.ar.data @= NastiReadAddressChannel(
nasti_params, 0, (req.addr >> b_len) << b_len, size, length)
tags_rdata = tags.read(idx)
self.io.nasti.aw.data @= NastiWriteAddressChannel(
nasti_params, 0,
m.bits(m.concat(idx, tags_rdata), nasti_params.x_addr_bits) <<
b_len, size, length)
self.io.nasti.w.data @= NastiWriteDataChannel(
nasti_params,
(read >> (m.zext_to(w_cnt, b_bits) *
nasti_params.x_data_bits))[:nasti_params.x_data_bits],
None, w_done)
self.io.nasti.w.valid @= state.O == State.WRITE
self.io.nasti.b.ready @= state.O == State.WRITE_ACK
self.io.nasti.r.ready @= state.O == State.READ
d_wen = m.Bit(name="d_wen")
d.write(True, idx, m.enable(d_wen))
data_wen = m.Bit(name="data_wen")
data_wdata = m.UInt[b_bits](name="data_wdata")
data.write(data_wdata, idx, m.enable(data_wen))
# m.display("data_wdata=%x", data_wdata).when(m.posedge(self.io.CLK))
v_wen = m.Bit(name="v_wen")
v.write(True, idx, m.enable(v_wen))
v_rdata = v.read(idx)
tags_wen = m.Bit(name="tags_wen")
tags.write(tag, idx, m.enable(tags_wen))
d_rdata = d.read(idx)
# m.display("gold_state=%x", state.O).when(m.posedge(self.io.CLK))
# m.display("gold_w_done=%x", w_done).when(m.posedge(self.io.CLK))
# m.display("gold_b_valid=%x",
# self.io.nasti.b.valid).when(m.posedge(self.io.CLK))
if TRACE:
m.display(
"[%0t] [cache] data[%x] <= %x, off: %x, req: %x, mask: %b",
m.time(), idx, write, off, self.io.req.data.data,
self.io.req.data.mask)\
.when(m.posedge(self.io.CLK))\
.if_((state.O == State.IDLE) &
(self.io.req.valid & self.io.resp.ready) &
(v_rdata & (tags_rdata == tag)) & req.mask.reduce_or())
m.display(
"[%0t] [cache] data[%x] => %x, off: %x, resp: %x", m.time(),
idx, write, off, self.io.resp.data.data.value())\
.when(m.posedge(self.io.CLK))\
.if_((state.O == State.IDLE) &
(self.io.req.valid & self.io.resp.ready) &
(v_rdata & (tags_rdata == tag)) & ~req.mask.reduce_or())
@m.inline_combinational()
def logic():
self.io.resp.valid @= False
self.io.req.ready @= False
self.io.nasti.ar.valid @= False
self.io.nasti.aw.valid @= False
d_wen @= False
data_wen @= False
data_wdata @= m.UInt[b_bits](0)
state.I @= state.O
tags_wen @= False
v_wen @= False
if state.O == State.IDLE:
if self.io.req.valid & self.io.resp.ready:
if v_rdata & (tags_rdata == tag):
if req.mask.reduce_or():
d_wen @= True
data_wdata @= write
data_wen @= True
self.io.req.ready @= True
self.io.resp.valid @= True
else:
if d_rdata:
self.io.nasti.aw.valid @= True
state.I @= State.WRITE
else:
data_wdata @= 0
data_wen @= True
self.io.nasti.ar.valid @= True
state.I @= State.READ
elif state.O == State.WRITE:
if w_done:
state.I @= State.WRITE_ACK
elif state.O == State.WRITE_ACK:
if self.io.nasti.b.valid:
data_wdata @= 0
data_wen @= True
self.io.nasti.ar.valid @= True
state.I @= State.READ
elif state.O == State.READ:
if self.io.nasti.r.valid:
data_wdata @= read | (
m.zext_to(self.io.nasti.r.data.data, b_bits) <<
(m.zext_to(r_cnt, b_bits) * nasti_params.x_data_bits))
data_wen @= True
if r_done:
tags_wen @= True
v_wen @= True
state.I @= State.IDLE
def __init__(self, x_len, n_ways: int, n_sets: int, b_bytes: int):
b_bits = b_bytes << 3
b_len = m.bitutils.clog2(b_bytes)
s_len = m.bitutils.clog2(n_sets)
t_len = x_len - (s_len + b_len)
n_words = b_bits // x_len
w_bytes = x_len // 8
byte_offset_bits = m.bitutils.clog2(w_bytes)
nasti_params = NastiParameters(data_bits=64,
addr_bits=x_len,
id_bits=5)
data_beats = b_bits // nasti_params.x_data_bits
class MetaData(m.Product):
tag = m.UInt[t_len]
self.io = m.IO(**make_cache_ports(x_len, nasti_params))
self.io += m.ClockIO()
class State(m.Enum):
IDLE = 0
READ_CACHE = 1
WRITE_CACHE = 2
WRITE_BACK = 3
WRITE_ACK = 4
REFILL_READY = 5
REFILL = 6
state = m.Register(init=State.IDLE)()
# memory
v = m.Register(m.UInt[n_sets], has_enable=True)()
d = m.Register(m.UInt[n_sets], has_enable=True)()
meta_mem = m.Memory(n_sets,
MetaData,
read_latency=1,
has_read_enable=True)()
data_mem = [
ArrayMaskMem(n_sets,
w_bytes,
m.UInt[8],
read_latency=1,
has_read_enable=True)() for _ in range(n_words)
]
addr_reg = m.Register(type(self.io.cpu.req.data.addr).undirected_t,
has_enable=True)()
cpu_data = m.Register(type(self.io.cpu.req.data.data).undirected_t,
has_enable=True)()
cpu_mask = m.Register(type(self.io.cpu.req.data.mask).undirected_t,
has_enable=True)()
self.io.nasti.r.ready @= state.O == State.REFILL
# Counters
assert data_beats > 0
if data_beats > 1:
read_counter = mantle.CounterModM(data_beats,
max(data_beats.bit_length(), 1),
has_ce=True)
read_counter.CE @= m.enable(self.io.nasti.r.fired())
read_count, read_wrap_out = read_counter.O, read_counter.COUT
write_counter = mantle.CounterModM(data_beats,
max(data_beats.bit_length(), 1),
has_ce=True)
write_count, write_wrap_out = write_counter.O, write_counter.COUT
else:
read_count, read_wrap_out = 0, 1
write_count, write_wrap_out = 0, 1
refill_buf = m.Register(m.Array[data_beats,
m.UInt[nasti_params.x_data_bits]],
has_enable=True)()
if data_beats == 1:
refill_buf.I[0] @= self.io.nasti.r.data.data
else:
refill_buf.I @= m.set_index(refill_buf.O,
self.io.nasti.r.data.data,
read_count[:-1])
refill_buf.CE @= m.enable(self.io.nasti.r.fired())
is_idle = state.O == State.IDLE
is_read = state.O == State.READ_CACHE
is_write = state.O == State.WRITE_CACHE
is_alloc = (state.O == State.REFILL) & read_wrap_out
# m.display("[%0t]: is_alloc = %x", m.time(), is_alloc)\
# .when(m.posedge(self.io.CLK))
is_alloc_reg = m.Register(m.Bit)()(is_alloc)
hit = m.Bit(name="hit")
wen = is_write & (hit | is_alloc_reg) & ~self.io.cpu.abort | is_alloc
# m.display("[%0t]: wen = %x", m.time(), wen)\
# .when(m.posedge(self.io.CLK))
ren = m.enable(~wen & (is_idle | is_read) & self.io.cpu.req.valid)
ren_reg = m.enable(m.Register(m.Bit)()(ren))
addr = self.io.cpu.req.data.addr
idx = addr[b_len:s_len + b_len]
tag_reg = addr_reg.O[s_len + b_len:x_len]
idx_reg = addr_reg.O[b_len:s_len + b_len]
off_reg = addr_reg.O[byte_offset_bits:b_len]
rmeta = meta_mem.read(idx, ren)
rdata = m.concat(*(mem.read(idx, ren) for mem in data_mem))
rdata_buf = m.Register(type(rdata), has_enable=True)()(rdata,
CE=ren_reg)
read = m.mux([
m.as_bits(m.mux([rdata_buf, rdata], ren_reg)),
m.as_bits(refill_buf.O)
], is_alloc_reg)
# m.display("is_alloc_reg=%x", is_alloc_reg)\
# .when(m.posedge(self.io.CLK))
hit @= v.O[idx_reg] & (rmeta.tag == tag_reg)
# read mux
self.io.cpu.resp.data.data @= m.array(
[read[i * x_len:(i + 1) * x_len] for i in range(n_words)])[off_reg]
self.io.cpu.resp.valid @= (is_idle | (is_read & hit) |
(is_alloc_reg & ~cpu_mask.O.reduce_or()))
m.display("resp.valid=%x", self.io.cpu.resp.valid.value())\
.when(m.posedge(self.io.CLK))
m.display("[%0t]: valid = %x", m.time(),
self.io.cpu.resp.valid.value())\
.when(m.posedge(self.io.CLK))
m.display("[%0t]: is_idle = %x, is_read = %x, hit = %x, is_alloc_reg = "
"%x, ~cpu_mask.O.reduce_or() = %x", m.time(), is_idle,
is_read, hit, is_alloc_reg, ~cpu_mask.O.reduce_or())\
.when(m.posedge(self.io.CLK))
m.display("[%0t]: refill_buf.O=%x, %x", m.time(), *refill_buf.O)\
.when(m.posedge(self.io.CLK))\
.if_(self.io.cpu.resp.valid.value() & is_alloc_reg)
m.display("[%0t]: read=%x", m.time(), read)\
.when(m.posedge(self.io.CLK))\
.if_(self.io.cpu.resp.valid.value() & is_alloc_reg)
addr_reg.I @= addr
addr_reg.CE @= m.enable(self.io.cpu.resp.valid.value())
cpu_data.I @= self.io.cpu.req.data.data
cpu_data.CE @= m.enable(self.io.cpu.resp.valid.value())
cpu_mask.I @= self.io.cpu.req.data.mask
cpu_mask.CE @= m.enable(self.io.cpu.resp.valid.value())
wmeta = MetaData(name="wmeta")
wmeta.tag @= tag_reg
offset_mask = (m.zext_to(cpu_mask.O, w_bytes * 8) << m.concat(
m.bits(0, byte_offset_bits), off_reg))
wmask = m.mux([m.SInt[w_bytes * 8](-1),
m.sint(offset_mask)], ~is_alloc)
if len(refill_buf.O) == 1:
wdata_alloc = self.io.nasti.r.data.data
else:
wdata_alloc = m.concat(
# TODO: not sure why they use `init.reverse`
# https://github.com/ucb-bar/riscv-mini/blob/release/src/main/scala/Cache.scala#L116
m.concat(*refill_buf.O[:-1]),
self.io.nasti.r.data.data)
wdata = m.mux([wdata_alloc,
m.as_bits(m.repeat(cpu_data.O, n_words))], ~is_alloc)
v.I @= m.set_index(v.O, m.bit(True), idx_reg)
v.CE @= m.enable(wen)
d.I @= m.set_index(d.O, ~is_alloc, idx_reg)
d.CE @= m.enable(wen)
# m.display("[%0t]: refill_buf.O = %x", m.time(),
# m.concat(*refill_buf.O)).when(m.posedge(self.io.CLK)).if_(wen)
# m.display("[%0t]: nasti.r.data.data = %x", m.time(),
# self.io.nasti.r.data.data).when(m.posedge(self.io.CLK)).if_(wen)
meta_mem.write(wmeta, idx_reg, m.enable(wen & is_alloc))
for i, mem in enumerate(data_mem):
data = [
wdata[i * x_len + j * 8:i * x_len + (j + 1) * 8]
for j in range(w_bytes)
]
mem.write(m.array(data), idx_reg,
wmask[i * w_bytes:(i + 1) * w_bytes], m.enable(wen))
# m.display("[%0t]: wdata = %x, %x, %x, %x", m.time(),
# *mem.WDATA.value()).when(m.posedge(self.io.CLK)).if_(wen)
# m.display("[%0t]: wmask = %x, %x, %x, %x", m.time(),
# *mem.WMASK.value()).when(m.posedge(self.io.CLK)).if_(wen)
tag_and_idx = m.zext_to(m.concat(idx_reg, tag_reg),
nasti_params.x_addr_bits)
self.io.nasti.ar.data @= NastiReadAddressChannel(
nasti_params, 0, tag_and_idx << m.Bits[len(tag_and_idx)](b_len),
m.bitutils.clog2(nasti_params.x_data_bits // 8), data_beats - 1)
rmeta_and_idx = m.zext_to(m.concat(idx_reg, rmeta.tag),
nasti_params.x_addr_bits)
self.io.nasti.aw.data @= NastiWriteAddressChannel(
nasti_params, 0,
rmeta_and_idx << m.Bits[len(rmeta_and_idx)](b_len),
m.bitutils.clog2(nasti_params.x_data_bits // 8), data_beats - 1)
self.io.nasti.w.data @= NastiWriteDataChannel(
nasti_params,
m.array([
read[i * nasti_params.x_data_bits:(i + 1) *
nasti_params.x_data_bits] for i in range(data_beats)
])[write_count[:-1]], None, write_wrap_out)
is_dirty = v.O[idx_reg] & d.O[idx_reg]
# TODO: Have to use temporary so we can invoke `fired()`
aw_valid = m.Bit(name="aw_valid")
self.io.nasti.aw.valid @= aw_valid
ar_valid = m.Bit(name="ar_valid")
self.io.nasti.ar.valid @= ar_valid
b_ready = m.Bit(name="b_ready")
self.io.nasti.b.ready @= b_ready
@m.inline_combinational()
def logic():
state.I @= state.O
aw_valid @= False
ar_valid @= False
self.io.nasti.w.valid @= False
b_ready @= False
if state.O == State.IDLE:
if self.io.cpu.req.valid:
if self.io.cpu.req.data.mask.reduce_or():
state.I @= State.WRITE_CACHE
else:
state.I @= State.READ_CACHE
elif state.O == State.READ_CACHE:
if hit:
if self.io.cpu.req.valid:
if self.io.cpu.req.data.mask.reduce_or():
state.I @= State.WRITE_CACHE
else:
state.I @= State.READ_CACHE
else:
state.I @= State.IDLE
else:
aw_valid @= is_dirty
ar_valid @= ~is_dirty
if self.io.nasti.aw.fired():
state.I @= State.WRITE_BACK
elif self.io.nasti.ar.fired():
state.I @= State.REFILL
elif state.O == State.WRITE_CACHE:
if hit | is_alloc_reg | self.io.cpu.abort:
state.I @= State.IDLE
else:
aw_valid @= is_dirty
ar_valid @= ~is_dirty
if self.io.nasti.aw.fired():
state.I @= State.WRITE_BACK
elif self.io.nasti.ar.fired():
state.I @= State.REFILL
elif state.O == State.WRITE_BACK:
self.io.nasti.w.valid @= True
if write_wrap_out:
state.I @= State.WRITE_ACK
elif state.O == State.WRITE_ACK:
b_ready @= True
if self.io.nasti.b.fired():
state.I @= State.REFILL_READY
elif state.O == State.REFILL_READY:
ar_valid @= True
if self.io.nasti.ar.fired():
state.I @= State.REFILL
elif state.O == State.REFILL:
if read_wrap_out:
if cpu_mask.O.reduce_or():
state.I @= State.WRITE_CACHE
else:
state.I @= State.IDLE
if data_beats > 1:
# TODO: Have to do this at the end since the inline comb logic
# wires up nasti.w
write_counter.CE @= m.enable(self.io.nasti.w.fired())