def to_circuit(self, char_in):
and_ = mantle.And(2)
ff = mantle.DFF()
m.wire(ff.O, and_.I0)
matcher = CharacterMatcher(self._c)
m.wire(char_in, matcher.char)
m.wire(matcher.match, and_.I1)
return (ff.I, and_.O)
def to_circuit(self, char_in):
(li, lo) = self._l.to_circuit(char_in)
(ri, ro) = self._l.to_circuit(char_in)
and_ = mantle.And(2)
and_(lo, ro)
b = m.Bit()
m.wire(b, li)
m.wire(b, ri)
return (b, and_.O)
def create_connect_box():
cb = m.DefineCircuit("connect_box",
"operand0", m.In(m.Bits(1)),
"operand1", m.In(m.Bits(1)),
"result", m.Out(m.Bits(1)),
"clk", m.In(m.Clock),
"rst", m.In(m.Reset),
"config_data", m.In(m.Bits(32)),
"config_en", m.In(m.Bit))
# Configuration data
config_reg = mantle.Register(32, init=0, has_ce=True, has_reset=True)
m.wire(cb.config_data, config_reg.I)
m.wire(cb.clk, config_reg.CLK)
m.wire(cb.config_en, config_reg.CE)
rst_inv = mantle.Invert(1)
m.wire(rst_inv.I[0], cb.rst)
m.wire(rst_inv.O[0], config_reg.RESET)
# Operations in CB
and_op = mantle.And(2, 1)
m.wire(cb.operand0, and_op.I0)
m.wire(cb.operand1, and_op.I1)
or_op = mantle.Or(2, 1)
m.wire(cb.operand0, or_op.I0)
m.wire(cb.operand1, or_op.I1)
xor_op = mantle.XOr(2, 1)
m.wire(cb.operand0, xor_op.I0)
m.wire(cb.operand1, xor_op.I1)
not_op = mantle.Invert(1)
m.wire(cb.operand0, not_op.I)
# Config mux
config_mux = mantle.Mux(height=4, width=1)
m.wire(config_mux.O, cb.result)
m.wire(config_mux.S, config_reg.O[0:2])
m.wire(and_op.O, config_mux.I0)
m.wire(or_op.O, config_mux.I1)
m.wire(xor_op.O, config_mux.I2)
m.wire(not_op.O, config_mux.I3)
return cb
def test_compile(caplog):
main = m.DefineCircuit("main", "I", m.In(m.Bits(2)), "O", m.Out(m.Bit))
and2 = mantle.And(2)
m.wire(main.I[0], and2.I0)
m.wire(main.I[1], and2.I1)
m.wire(and2.O, main.O)
m.EndCircuit()
m.compile("build/test_coreir_compile_verilog", main)
assert check_files_equal(__file__, "build/test_coreir_compile_verilog.v",
"gold/test_coreir_compile_verilog.v")
assert caplog.records[
0].msg == "`m.compile` called with `output == verilog` and `m.mantle_target == \"coreir\"` and mantle has been imported, When generating verilog from circuits from the \"coreir\" mantle target, you should set `output=\"coreir-verilog\"`. Doing this automatically."
def definition(io):
# Configuration data
config_reg = mantle.Register(32,
init=0,
has_ce=True,
has_reset=True)
m.wire(io.config_data, config_reg.I)
m.wire(io.clk, config_reg.CLK)
m.wire(io.config_en, config_reg.CE)
rst_inv = mantle.Invert(1)
m.wire(rst_inv.I[0], io.rst)
m.wire(rst_inv.O[0], config_reg.RESET)
# Operations in CLB
and_op = mantle.And(2, 1)
m.wire(io.operand0, and_op.I0)
m.wire(io.operand1, and_op.I1)
or_op = mantle.Or(2, 1)
m.wire(io.operand0, or_op.I0)
m.wire(io.operand1, or_op.I1)
xor_op = mantle.XOr(2, 1)
m.wire(io.operand0, xor_op.I0)
m.wire(io.operand1, xor_op.I1)
not_op = mantle.Invert(1)
m.wire(io.operand0, not_op.I)
# Config mux
config_mux = mantle.Mux(height=4, width=1)
m.wire(config_mux.O, io.result)
m.wire(config_mux.S, config_reg.O[0:2])
m.wire(and_op.O, config_mux.I0)
m.wire(or_op.O, config_mux.I1)
m.wire(xor_op.O, config_mux.I2)
m.wire(not_op.O, config_mux.I3)
def definition(io):
# IF - get cycle_id, label_index_id
controller = Controller()
reg_1_cycle = mantle.Register(n)
reg_1_control = mantle.DFF(init=1)
wire(io.CLK, controller.CLK)
wire(io.CLK, reg_1_cycle.CLK)
wire(io.CLK, reg_1_control.CLK)
reg_1_idx = controller.IDX
wire(controller.CYCLE, reg_1_cycle.I)
wire(1, reg_1_control.I)
# RR - get weight block, image block of N bits
readROM = ReadROM()
wire(reg_1_idx, readROM.IDX)
wire(reg_1_cycle.O, readROM.CYCLE)
reg_2 = mantle.Register(N + b + n)
reg_2_control = mantle.DFF()
reg_2_weight = readROM.WEIGHT
wire(io.CLK, reg_2.CLK)
wire(io.CLK, readROM.CLK)
wire(io.CLK, reg_2_control.CLK)
wire(readROM.IMAGE, reg_2.I[:N])
wire(reg_1_idx, reg_2.I[N:N + b])
wire(reg_1_cycle.O, reg_2.I[N + b:])
wire(reg_1_control.O, reg_2_control.I)
# EX - NXOr for multiplication, pop count and accumulate the result for activation
multiplier = mantle.NXOr(height=2, width=N)
bit_counter = DefineBitCounter(N)()
adder = mantle.Add(n_bc_adder, cin=False, cout=False)
mux_for_adder_0 = mantle.Mux(height=2, width=n_bc_adder)
mux_for_adder_1 = mantle.Mux(height=2, width=n_bc_adder)
reg_3_1 = mantle.Register(n_bc_adder)
reg_3_2 = mantle.Register(b + n)
wire(io.CLK, reg_3_1.CLK)
wire(io.CLK, reg_3_2.CLK)
wire(reg_2_weight, multiplier.I0)
wire(reg_2.O[:N], multiplier.I1)
wire(multiplier.O, bit_counter.I)
wire(bits(0, n_bc_adder), mux_for_adder_0.I0)
wire(bit_counter.O, mux_for_adder_0.I1[:n_bc])
if n_bc_adder > n_bc:
wire(bits(0, n_bc_adder - n_bc), mux_for_adder_0.I1[n_bc:])
# only when data read is ready (i.e. control signal is high), accumulate the pop count result
wire(reg_2_control.O, mux_for_adder_0.S)
wire(reg_3_1.O, mux_for_adder_1.I0)
wire(bits(0, n_bc_adder), mux_for_adder_1.I1)
if n == 4:
comparison_3 = SB_LUT4(LUT_INIT=int('0' * 15 + '1', 2))
wire(
reg_2.O[N + b:],
bits([
comparison_3.I0, comparison_3.I1, comparison_3.I2,
comparison_3.I3
]))
else:
comparison_3 = mantle.EQ(n)
wire(reg_2.O[N + b:], comparison_3.I0)
wire(bits(0, n), comparison_3.I1)
wire(comparison_3.O, mux_for_adder_1.S)
wire(mux_for_adder_0.O, adder.I0)
wire(mux_for_adder_1.O, adder.I1)
wire(adder.O, reg_3_1.I)
wire(reg_2.O[N:], reg_3_2.I)
# CF - classify the image
classifier = Classifier()
reg_4 = mantle.Register(n + b)
reg_4_idx = classifier.O
wire(io.CLK, classifier.CLK)
wire(io.CLK, reg_4.CLK)
wire(reg_3_1.O, classifier.I)
wire(reg_3_2.O[:b], classifier.IDX)
wire(reg_3_2.O, reg_4.I)
# WB - wait to show the result until the end
reg_5 = mantle.Register(b, has_ce=True)
comparison_5_1 = mantle.EQ(b)
comparison_5_2 = mantle.EQ(n)
and_gate = mantle.And()
wire(io.CLK, reg_5.CLK)
wire(reg_4_idx, reg_5.I)
wire(reg_4.O[:b], comparison_5_1.I0)
wire(bits(num_classes - 1, b), comparison_5_1.I1)
wire(reg_4.O[b:], comparison_5_2.I0)
wire(bits(num_cycles - 1, n), comparison_5_2.I1)
wire(comparison_5_1.O, and_gate.I0)
wire(comparison_5_2.O, and_gate.I1)
wire(and_gate.O, reg_5.CE)
wire(reg_5.O, io.O)
# latch the light indicating the end
reg_6 = mantle.DFF()
wire(io.CLK, reg_6.CLK)
or_gate = mantle.Or()
wire(and_gate.O, or_gate.I0)
wire(reg_6.O, or_gate.I1)
wire(or_gate.O, reg_6.I)
wire(reg_6.O, io.D)
def create_pe_tile():
pe = m.DefineCircuit(
"pe_tile", "clk", m.In(m.Clock), "rst", m.In(m.Reset), "config_data",
m.In(m.Bits(32)), "config_addr", m.In(m.Bits(32)), "tile_id",
m.In(m.Bits(16)), "side_0_track_0_in", m.In(m.Bits(1)),
"side_0_track_1_in", m.In(m.Bits(1)), "side_0_track_2_in",
m.In(m.Bits(1)), "side_0_track_3_in", m.In(m.Bits(1)),
"side_1_track_0_in", m.In(m.Bits(1)), "side_1_track_1_in",
m.In(m.Bits(1)), "side_1_track_2_in", m.In(m.Bits(1)),
"side_1_track_3_in", m.In(m.Bits(1)), "side_2_track_0_in",
m.In(m.Bits(1)), "side_2_track_1_in", m.In(m.Bits(1)),
"side_2_track_2_in", m.In(m.Bits(1)), "side_2_track_3_in",
m.In(m.Bits(1)), "side_3_track_0_in", m.In(m.Bits(1)),
"side_3_track_1_in", m.In(m.Bits(1)), "side_3_track_2_in",
m.In(m.Bits(1)), "side_3_track_3_in", m.In(m.Bits(1)),
"side_0_track_0_out", m.Out(m.Bits(1)), "side_0_track_1_out",
m.Out(m.Bits(1)), "side_0_track_2_out", m.Out(m.Bits(1)),
"side_0_track_3_out", m.Out(m.Bits(1)), "side_1_track_0_out",
m.Out(m.Bits(1)), "side_1_track_1_out", m.Out(m.Bits(1)),
"side_1_track_2_out", m.Out(m.Bits(1)), "side_1_track_3_out",
m.Out(m.Bits(1)), "side_2_track_0_out", m.Out(m.Bits(1)),
"side_2_track_1_out", m.Out(m.Bits(1)), "side_2_track_2_out",
m.Out(m.Bits(1)), "side_2_track_3_out", m.Out(m.Bits(1)),
"side_3_track_0_out", m.Out(m.Bits(1)), "side_3_track_1_out",
m.Out(m.Bits(1)), "side_3_track_2_out", m.Out(
m.Bits(1)), "side_3_track_3_out", m.Out(m.Bits(1)))
# Configuration data
config_reg = mantle.Register(32, init=0, has_ce=True, has_reset=True)
addr_match = mantle.EQ(16)
m.wire(addr_match.I0, pe.config_addr[0:16])
m.wire(addr_match.I1, pe.tile_id)
m.wire(addr_match.O, config_reg.CE)
m.wire(pe.config_data, config_reg.I)
m.wire(pe.clk, config_reg.CLK)
rst_inv = mantle.Invert(1)
m.wire(rst_inv.I[0], pe.rst)
m.wire(rst_inv.O[0], config_reg.RESET)
# Configure sb = 6, cb0 = 4, cb1 = 5, clb = 7
config_cb0_eq = mantle.EQ(16)
m.wire(m.uint(4, 16), config_cb0_eq.I0)
m.wire(pe.config_addr[16:32], config_cb0_eq.I1)
config_cb1_eq = mantle.EQ(16)
m.wire(m.uint(5, 16), config_cb1_eq.I0)
m.wire(pe.config_addr[16:32], config_cb1_eq.I1)
config_clb_eq = mantle.EQ(16)
m.wire(m.uint(7, 16), config_clb_eq.I0)
m.wire(pe.config_addr[16:32], config_clb_eq.I1)
config_sb_eq = mantle.EQ(16)
m.wire(m.uint(6, 16), config_sb_eq.I0)
m.wire(pe.config_addr[16:32], config_sb_eq.I1)
config_cb0 = mantle.And(2, 1)
m.wire(config_cb0.I0[0], config_cb0_eq.O)
m.wire(config_cb0.I1[0], addr_match.O)
config_cb1 = mantle.And(2, 1)
m.wire(config_cb1.I0[0], config_cb1_eq.O)
m.wire(config_cb1.I1[0], addr_match.O)
config_clb = mantle.And(2, 1)
m.wire(config_clb.I0[0], config_clb_eq.O)
m.wire(config_clb.I1[0], addr_match.O)
config_sb = mantle.And(2, 1)
m.wire(config_sb.I0[0], config_sb_eq.O)
m.wire(config_sb.I1[0], addr_match.O)
# Add ands!
# # CB0
cb0 = create_connect_box(1)()
m.wire(pe.clk, cb0.clk)
m.wire(pe.rst, cb0.rst)
m.wire(pe.config_data, cb0.config_data)
m.wire(config_cb0.O[0], cb0.config_en)
# CB1
cb1 = create_connect_box(1)()
m.wire(pe.clk, cb1.clk)
m.wire(pe.rst, cb1.rst)
m.wire(pe.config_data, cb1.config_data)
m.wire(config_cb1.O[0], cb1.config_en)
# CLB
clb = create_clb(1)()
m.wire(pe.clk, clb.clk)
m.wire(pe.rst, clb.rst)
m.wire(pe.config_data, clb.config_data)
m.wire(config_clb.O[0], clb.config_en)
# Switch box
sb = create_switch_box(1)()
m.wire(pe.clk, sb.clk)
m.wire(pe.rst, sb.rst)
m.wire(pe.config_data, sb.config_data)
m.wire(config_sb.O[0], sb.config_en)
m.wire(clb.result, sb.clb_result)
for side in range(0, 4):
for track in range(0, 4):
m.wire(
getattr(pe,
'side_' + str(side) + '_track_' + str(track) + '_in'),
getattr(sb,
'side_' + str(side) + '_track_' + str(track) + '_in'))
for side in range(0, 4):
for track in range(0, 4):
m.wire(
getattr(pe,
'side_' + str(side) + '_track_' + str(track) + '_out'),
getattr(sb,
'side_' + str(side) + '_track_' + str(track) + '_out'))
# Wiring up CLB, SB and CBs
m.wire(pe.side_0_track_0_in, cb0.track_0_in)
m.wire(pe.side_0_track_1_in, cb0.track_1_in)
m.wire(pe.side_0_track_2_in, cb0.track_2_in)
m.wire(pe.side_0_track_3_in, cb0.track_3_in)
m.wire(sb.side_0_track_0_out, cb0.track_0_out)
m.wire(sb.side_0_track_1_out, cb0.track_1_out)
m.wire(sb.side_0_track_2_out, cb0.track_2_out)
m.wire(sb.side_0_track_3_out, cb0.track_3_out)
m.wire(cb0.out, clb.operand0)
m.wire(pe.side_1_track_0_in, cb1.track_0_in)
m.wire(pe.side_1_track_1_in, cb1.track_1_in)
m.wire(pe.side_1_track_2_in, cb1.track_2_in)
m.wire(pe.side_1_track_3_in, cb1.track_3_in)
m.wire(sb.side_1_track_0_out, cb1.track_0_out)
m.wire(sb.side_1_track_1_out, cb1.track_1_out)
m.wire(sb.side_1_track_2_out, cb1.track_2_out)
m.wire(sb.side_1_track_3_out, cb1.track_3_out)
m.wire(cb1.out, clb.operand1)
m.EndDefine()
return pe
def definition(io):
feedthrough_count = num_tracks
for i in range(0, len(feedthrough_outputs)):
feedthrough_count -= feedthrough_outputs[i] == '1'
mux_sel_bit_count = int(
math.ceil(
math.log(num_tracks - feedthrough_count + has_constant,
2)))
constant_bit_count = has_constant * width
config_bit_count = mux_sel_bit_count + constant_bit_count
config_reg_width = int(math.ceil(config_bit_count / 32.0) * 32)
reset_val = num_tracks - feedthrough_count + has_constant - 1
config_reg_reset_bit_vector = []
CONFIG_DATA_WIDTH = 32
if (constant_bit_count > 0):
print('constant_bit_count =', constant_bit_count)
reset_bits = m.bitutils.int2seq(default_value,
constant_bit_count)
default_bits = m.bitutils.int2seq(reset_val, mux_sel_bit_count)
print('default val bits =', reset_bits)
print('reset val bits =', default_bits)
# concat before assert
config_reg_reset_bit_vector += default_bits
config_reg_reset_bit_vector += reset_bits
config_reg_reset_bit_vector = \
m.bitutils.seq2int(config_reg_reset_bit_vector)
print('reset bit vec as int =', config_reg_reset_bit_vector)
else:
config_reg_reset_bit_vector = reset_val
config_cb = mantle.Register(config_reg_width,
init=config_reg_reset_bit_vector,
has_ce=True,
has_reset=True)
config_addr_zero = mantle.EQ(8)
m.wire(m.uint(0, 8), config_addr_zero.I0)
m.wire(config_addr_zero.I1, io.config_addr[24:32])
config_en_set = mantle.And(2, 1)
m.wire(config_en_set.I0, m.uint(1, 1))
m.wire(config_en_set.I1[0], io.config_en)
config_en_set_and_addr_zero = mantle.And(2, 1)
m.wire(config_en_set_and_addr_zero.I0, config_en_set.O)
m.wire(config_en_set_and_addr_zero.I1[0], config_addr_zero.O)
m.wire(config_en_set_and_addr_zero.O[0], config_cb.CE)
config_set_mux = mantle.Mux(height=2, width=CONFIG_DATA_WIDTH)
m.wire(config_set_mux.I0, config_cb.O)
m.wire(config_set_mux.I1, io.config_addr)
m.wire(config_set_mux.S, config_en_set_and_addr_zero.O[0])
m.wire(config_cb.RESET, io.reset)
m.wire(config_cb.I, io.config_data)
# Setting read data
read_data_mux = mantle.Mux(height=2, width=CONFIG_DATA_WIDTH)
m.wire(read_data_mux.S,
equals_cmp(io.config_addr[24:32], m.uint(0, 8), 8).O)
m.wire(read_data_mux.I1, config_cb.O)
m.wire(read_data_mux.I0, m.uint(0, 32))
m.wire(io.read_data, read_data_mux.O)
pow_2_tracks = power_log(num_tracks)
print('# of tracks =', pow_2_tracks)
output_mux = mantle.Mux(height=pow_2_tracks, width=width)
m.wire(output_mux.S, config_cb.O[0:math.ceil(math.log(width, 2))])
# Note: Uncomment this line for select to make the unit test fail!
# m.wire(output_mux.S, m.uint(0, math.ceil(math.log(width, 2))))
# This is only here because this is the way the switch box numbers
# things.
# We really should get rid of this feedthrough parameter
sel_out = 0
for i in range(0, pow_2_tracks):
# in_track = 'I' + str(i)
if (i < num_tracks):
if (feedthrough_outputs[i] == '1'):
m.wire(getattr(output_mux, 'I' + str(sel_out)),
getattr(io, 'in_' + str(i)))
sel_out += 1
if (has_constant == 0):
while (sel_out < pow_2_tracks):
m.wire(getattr(output_mux, 'I' + str(sel_out)),
m.uint(0, width))
sel_out += 1
else:
const_val = config_cb.O[mux_sel_bit_count:mux_sel_bit_count +
constant_bit_count]
while (sel_out < pow_2_tracks):
m.wire(getattr(output_mux, 'I' + str(sel_out)), const_val)
sel_out += 1
# NOTE: This is a dummy! fix it later!
m.wire(output_mux.O, io.out)
return
