def __init__(self, romfile = './roms/tec1a.rom'):
self.rom = memory.rom(11)
self.rom.load_file(0, romfile)
self.ram = memory.ram(11)
self.empty = memory.null()
def __init__(self, romfile = './roms/ace.rom'):
self.rom = memory.rom(13)
self.rom.load_file(0, romfile)
self.video = memory.ram(10)
self.char = memory.wom(10)
self.ram = memory.ram(10)
self.empty = memory.null()
def emit_opcode_table(out, idic, prefix, links, preamble):
"""emit a function table for each opcode with this prefix"""
out.indent(2)
label = '_%s' % ''.join(['%02x' % byte for byte in prefix])
out.put('self.opcodes%s = (\n' % (label, '')[len(label) == 1])
out.indent(1)
for opcode in range(0x100):
code = list(prefix)
code.append(opcode)
# disassemble the instruction
mem = memory.ram(4)
mem.load(0, code)
(operation, operands, nbytes) = z80da.disassemble(mem, 0)
# add the instruction to the dictionary
inst = ' '.join((operation, operands))
label = ''.join(['%02x' % byte for byte in code])
if opcode in links:
out.put('self._execute_%s,' % label)
out.pad(36)
out.put('# 0x%02x execute %s prefix\n' % (opcode, label))
else:
# add the inst/label to the dictionary if it is unique
if idic.has_key(inst) == False:
idic[inst] = (label, code, preamble)
out.put('self._ins_%s,' % idic[inst][0])
out.pad(36)
out.put('# 0x%02x %s\n' % (opcode, inst))
out.outdent(1)
out.put(')\n')
out.outdent(2)
def emit_opcode_table(out, idic, prefix, links, preamble):
"""emit a function table for each opcode with this prefix"""
out.indent(2)
label = '_%s' % ''.join(['%02x' % byte for byte in prefix])
out.put('self.opcodes%s = (\n' % (label, '')[len(label) == 1])
out.indent(1)
for opcode in range(0x100):
code = list(prefix)
code.append(opcode)
# disassemble the instruction
mem = memory.ram(4)
mem.load(0, code)
(operation, operands, nbytes) = z80da.disassemble(mem, 0)
# add the instruction to the dictionary
inst = ' '.join((operation, operands))
label = ''.join(['%02x' % byte for byte in code])
if opcode in links:
out.put('self._execute_%s,' % label)
out.pad(36)
out.put('# 0x%02x execute %s prefix\n' % (opcode, label))
else:
# add the inst/label to the dictionary if it is unique
if idic.has_key(inst) == False:
idic[inst] = (label, code, preamble)
out.put('self._ins_%s,' % idic[inst][0])
out.pad(36)
out.put('# 0x%02x %s\n' % (opcode, inst))
out.outdent(1)
out.put(')\n')
out.outdent(2)
def test_ram(self):
bits = 10
size = 1 << bits
val = 0xab
ram = memory.ram(bits)
self.assertEqual(ram[0], 0)
ram[0] = val
self.assertEqual(ram[0], val)
self.assertEqual(ram[0 + size], val)
self.assertEqual(ram[10], 0)
ram[10] = val
self.assertEqual(ram[10 + size], val)
def test_ram(self):
bits = 10
size = 1 << bits
val = 0xab
ram = memory.ram(bits)
self.assertEqual(ram[0], 0)
ram[0] = val
self.assertEqual(ram[0], val)
self.assertEqual(ram[0 + size], val)
self.assertEqual(ram[10], 0)
ram[10] = val
self.assertEqual(ram[10 + size], val)
def test_regs(self):
mem = memory.ram(4)
cpu = z80.cpu(mem, None)
cpu.set_af(0x0123)
cpu.set_bc(0x4567)
cpu.set_de(0x89ab)
cpu.set_hl(0xcdef)
self.assertEqual(cpu.a, 0x01)
self.assertEqual(cpu.f.get(), 0x23)
self.assertEqual(cpu.b, 0x45)
self.assertEqual(cpu.c, 0x67)
self.assertEqual(cpu.d, 0x89)
self.assertEqual(cpu.e, 0xab)
self.assertEqual(cpu.h, 0xcd)
self.assertEqual(cpu.l, 0xef)
def test_regs(self):
mem = memory.ram(4)
cpu = z80.cpu(mem, None)
cpu.set_af(0x0123)
cpu.set_bc(0x4567)
cpu.set_de(0x89ab)
cpu.set_hl(0xcdef)
self.assertEqual(cpu.a, 0x01)
self.assertEqual(cpu.f.get(), 0x23)
self.assertEqual(cpu.b, 0x45)
self.assertEqual(cpu.c, 0x67)
self.assertEqual(cpu.d, 0x89)
self.assertEqual(cpu.e, 0xab)
self.assertEqual(cpu.h, 0xcd)
self.assertEqual(cpu.l, 0xef)
