def digitalWrite(gpio_pin, state): """ Writes given digital pin low if state=0, high otherwise. """ assert (gpio_pin in GPIO), "*Invalid GPIO pin: '%s'" % gpio_pin if (state): memory.setReg(GPIO[gpio_pin][0]+GPIO_SETDATAOUT, GPIO[gpio_pin][1]) else: memory.setReg(GPIO[gpio_pin][0]+GPIO_CLEARDATAOUT, GPIO[gpio_pin][1])
def pwm_init(): # Enable EHRPWM module clocks: memory.setReg(CM_PER_EPWMSS1_CLKCTRL, MODULEMODE_ENABLE) # Wait for enable complete: while (memory.getReg(CM_PER_EPWMSS1_CLKCTRL) & IDLEST_MASK): delay(1) memory.setReg(CM_PER_EPWMSS2_CLKCTRL, MODULEMODE_ENABLE) # Wait for enable complete: while (memory.getReg(CM_PER_EPWMSS2_CLKCTRL) & IDLEST_MASK): delay(1)
def analogRead(analog_pin): """ Returns analog value read on given analog input pin. """ assert (analog_pin in ADC), "*Invalid analog pin: '%s'" % analog_pin if (memory.getReg(CM_WKUP_ADC_TSC_CLKCTRL) & IDLEST_MASK): # The ADC module clock has been shut off, e.g. by a different # PyBBIO script stopping while this one was running, turn back on: analog_init() # Enable sequncer step that's set for given input: memory.setReg(ADC_STEPENABLE, ADC_ENABLE(analog_pin)) # Sequencer starts automatically after enabling step, wait for complete: while(memory.getReg(ADC_STEPENABLE) & ADC_ENABLE(analog_pin)): pass # Return 12-bit value from the ADC FIFO register: return memory.getReg(ADC_FIFO0DATA) & ADC_FIFO_MASK
def analog_init(): """ Initializes the on-board 8ch 12bit ADC. """ # Enable ADC module clock, though should already be enabled on # newer Angstrom images: memory.setReg(CM_WKUP_ADC_TSC_CLKCTRL, MODULEMODE_ENABLE) # Wait for enable complete: while (memory.getReg(CM_WKUP_ADC_TSC_CLKCTRL) & IDLEST_MASK): delay(1) # Software reset: memory.setReg(ADC_SYSCONFIG, ADC_SOFTRESET) while(memory.getReg(ADC_SYSCONFIG) & ADC_SOFTRESET): pass # Make sure STEPCONFIG write protect is off: memory.setReg(ADC_CTRL, ADC_STEPCONFIG_WRITE_PROTECT_OFF) # Set STEPCONFIG1-STEPCONFIG8 to correspond to ADC inputs 0-7: for i in xrange(8): config = SEL_INP('AIN%i' % i) | ADC_AVG2 memory.setReg(eval('ADCSTEPCONFIG%i' % (i+1)), config) memory.setReg(eval('ADCSTEPDELAY%i' % (i+1)), SAMPLE_DELAY(15)) # Now we can enable ADC subsystem, leaving write protect off: memory.orReg(ADC_CTRL, TSC_ADC_SS_ENABLE)
def analog_cleanup(): # Software reset: memory.setReg(ADC_SYSCONFIG, ADC_SOFTRESET) while(memory.getReg(ADC_SYSCONFIG) & ADC_SOFTRESET): pass
def analog_cleanup(): # Software reset: memory.setReg(ADC_SYSCONFIG, ADC_SOFTRESET) while (memory.getReg(ADC_SYSCONFIG) & ADC_SOFTRESET): pass