def __init__(self,
platform,
clk_name,
rst_name,
period=None,
rst_invert=False):
SimpleCRG.__init__(self, platform, clk_name, rst_name, rst_invert)
_add_period_constraint(platform, self._clk, period)
def __init__(self):
XilinxISEPlatform.__init__(
self, "xc6slx9-2csg324", _io,
lambda p: SimpleCRG(p, "clk_y3", "user_btn"))
self.add_platform_command("""
CONFIG VCCAUX = "3.3";
""")
def __init__(self, manual_timing=False, extra_io=[]):
io = _io + extra_io
self.manual_timing = manual_timing
XilinxISEPlatform.__init__(self, "xc6slx150-3csg484", io,
lambda p: SimpleCRG(p, "clk_if", None))
self.add_platform_command("""
CONFIG VCCAUX = "2.5";
""")
def __init__(self, platform, clk_name, rst_name, period=None, rst_invert=False): SimpleCRG.__init__(self, platform, clk_name, rst_name, rst_invert) _add_period_constraint(platform, self._clk, period)
def __init__(self):
XilinxISEPlatform.__init__(self, "xc3s200a-ft256-4", _ios,
lambda p: SimpleCRG(p, "clk0", None),
_connectors)
def __init__(self):
XilinxISEPlatform.__init__(self, "xc6slx150-3csg484", _io,
lambda p: SimpleCRG(p, "clk_if", "rst"))
self.add_platform_command("""
CONFIG VCCAUX = "2.5";
""")
def __init__(self): XilinxISEPlatform.__init__(self, "xc6slx45-fgg484-2", _io, lambda p: SimpleCRG(p, "clk50", None))
def __init__(self): XilinxISEPlatform.__init__(self, "xc6slx9-2csg225", _ios, lambda p: SimpleCRG(p, "clk3", None), _connectors)
def __init__(self):
XilinxISEPlatform.__init__(self, "xc6slx45-fgg484-2", self._io,
lambda p: SimpleCRG(p, "clk", "rst"))
def __init__(self):
XilinxISEPlatform.__init__(self, "xc6slx9-tqg144-3", _io,
lambda p: SimpleCRG(p, "clk50", None))
def __init__(self):
AlteraQuartusPlatform.__init__(self, "EP4CE22F17C6", _io,
lambda p: SimpleCRG(p, "clk50", None))
def __init__(self):
XilinxISEPlatform.__init__(self, "xc6slx45-fgg484-2", _io,
lambda p: SimpleCRG(p, "clk50", None))
self.add_platform_command("CONFIG VCCAUX=\"3.3\";\n")
def __init__(self, platform, clk_name, rst_name, period, rst_invert=False): SimpleCRG.__init__(self, platform, clk_name, rst_name, rst_invert) platform.add_period_constraint(platform, self.cd_sys.clk, period)
def __init__(self): XilinxISEPlatform.__init__(self, "xc7z020-clg484-1", _io, lambda p: SimpleCRG(p, "clk100", None))
def __init__(self): XilinxISEPlatform.__init__(self, "xc6slx9-tqg144-2", _io, lambda p: SimpleCRG(p, "clk32", None), _connectors)