def __init__(self, programmer="openocd"):
# XC6SLX45-2CSG324C
XilinxPlatform.__init__(self, "xc6slx45-csg324-3", _io, _connectors)
self.programmer = programmer
# FPGA AUX is connected to the 2.5V supply on the Atlys
self.add_platform_command("""CONFIG VCCAUX="2.5";""")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
self.add_platform_command("""
TIMESPEC TS_Pad2Pad = FROM PADS TO PADS 7 ns;
""")
try:
ifclk = self.lookup_request("fx2_ifclk")
gpif = self.lookup_request("fx2_gpif")
for i, d in [(gpif.d, "in"), (gpif.d, "out"),
(gpif.ctl, "in"), (gpif.adr, "out"),
(gpif.slwr, "out"), (gpif.sloe, "out"),
(gpif.slrd, "out"), (gpif.pktend, "out")]:
if flen(i) > 1:
q = "(*)"
else:
q = ""
self.add_platform_command("""
INST "{i}%s" TNM = gpif_net_%s;
""" % (q, d), i=i)
self.add_platform_command("""
NET "{ifclk}" TNM_NET = "GRPifclk";
TIMESPEC "TSifclk" = PERIOD "GRPifclk" 20833 ps HIGH 50%;
TIMEGRP "gpif_net_in" OFFSET = IN 5 ns VALID 10 ns BEFORE "{ifclk}" RISING;
TIMEGRP "gpif_net_out" OFFSET = OUT 7 ns AFTER "{ifclk}" RISING;
""", ifclk=ifclk)
except ConstraintError:
pass
def __init__(self, programmer="xc3sprog"):
# XC6SLX45-2CSG324C
XilinxPlatform.__init__(self, "xc6slx45-csg324-3", _io, _connectors)
self.programmer = programmer
# FPGA AUX is connected to the 2.5V supply on the Atlys
self.add_platform_command("""CONFIG VCCAUX="2.5";""")
def __init__(self):
XilinxPlatform.__init__(self, "xc6slx9-2csg324", _io)
self.add_platform_command("""
CONFIG VCCAUX = "3.3";
""")
self.toolchain.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g SPI_buswidth:4"
self.toolchain.ise_commands = """
def __init__(self):
XilinxPlatform.__init__(self, "xc3s500e-4pq208", _io)
self.toolchain.xst_opt = """-ifmt MIXED
-opt_level 2
-opt_mode SPEED
-register_balancing yes"""
self.toolchain.bitgen_opt += (" -g GTS_cycle:3 -g LCK_cycle:4 "
"-g GWE_cycle:5 -g DONE_cycle:6")
self.toolchain.ise_commands += """
def __init__(self):
XilinxPlatform.__init__(self, "xc3s500e-4pq208", _io)
self.toolchain.xst_opt = """-ifmt MIXED
-opt_level 2
-opt_mode SPEED
-register_balancing yes"""
self.toolchain.bitgen_opt += (" -g GTS_cycle:3 -g LCK_cycle:4 "
"-g GWE_cycle:5 -g DONE_cycle:6")
self.toolchain.ise_commands += """
def __init__(self, toolchain="vivado", programmer="xc3sprog"):
XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors,
toolchain=toolchain)
if toolchain == "ise":
self.toolchain.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g ConfigRate:12 -g SPI_buswidth:4"
elif toolchain == "vivado":
self.toolchain.bitstream_commands = ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
self.programmer = programmer
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
try:
self.add_period_constraint(self.lookup_request("hdmi_in", 0).clk_p, 12)
except ConstraintError:
pass
try:
self.add_period_constraint(self.lookup_request("clk50", 0), 20)
except ConstraintError:
pass
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
try:
self.add_period_constraint(
self.lookup_request("hdmi_in", 0).clk_p, 12)
except ConstraintError:
pass
try:
self.add_period_constraint(self.lookup_request("clk50", 0), 20)
except ConstraintError:
pass
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
try:
eth_clocks = self.lookup_request("eth_clocks")
self.add_period_constraint(eth_clocks.rx, 40)
self.add_period_constraint(eth_clocks.tx, 40)
self.add_platform_command("""
TIMESPEC "TS{phy_tx_clk}_io" = FROM "GRP{phy_tx_clk}" TO "PADS" 10 ns;
TIMESPEC "TS{phy_rx_clk}_io" = FROM "PADS" TO "GRP{phy_rx_clk}" 10 ns;
""", phy_rx_clk=eth_clocks.rx, phy_tx_clk=eth_clocks.tx)
except ConstraintError:
pass
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
try:
self.add_period_constraint(self.lookup_request("clk200").p, 5.0)
except ConstraintError:
pass
try:
self.add_period_constraint(self.lookup_request("eth_clocks").rx, 8.0)
except ConstraintError:
pass
if isinstance(self.toolchain, XilinxISEToolchain):
self.add_platform_command("CONFIG DCI_CASCADE = \"33 32 34\";")
else:
self.add_platform_command("set_property DCI_CASCADE {{32 34}} [get_iobanks 33]")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
try:
clk_if = self.lookup_request("clk_if")
clk_fx = self.lookup_request("clk_fx")
self.add_platform_command("""
NET "{clk_if}" TNM_NET = "GRPclk_if";
NET "{clk_fx}" TNM_NET = "GRPclk_fx";
TIMESPEC "TSclk_fx" = PERIOD "GRPclk_fx" 20.83333 ns HIGH 50%;
TIMESPEC "TSclk_if" = PERIOD "GRPclk_if" 20 ns HIGH 50%;
TIMESPEC "TSclk_fx2if" = FROM "GRPclk_fx" TO "GRPclk_if" 3 ns DATAPATHONLY;
TIMESPEC "TSclk_if2fx" = FROM "GRPclk_if" TO "GRPclk_fx" 3 ns DATAPATHONLY;
""", clk_if=clk_if, clk_fx=clk_fx)
except ConstraintError:
pass
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
for i in range(2):
try:
self.add_period_constraint(self.lookup_request("hdmi_in", i).clk_p, 12)
except ConstraintError:
pass
try:
self.add_period_constraint(self.lookup_request("eth_clocks").rx, 40.0)
except ConstraintError:
pass
try:
self.add_period_constraint(self.lookup_request("fx2").ifclk, 20.8)
except ConstraintError:
pass
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
for i in range(2):
try:
self.add_period_constraint(self.lookup_request("hdmi_in", i).clk_p, 12)
except ConstraintError:
pass
try:
self.add_period_constraint(self.lookup_request("eth_clocks").rx, 40.0)
except ConstraintError:
pass
try:
self.add_period_constraint(self.lookup_request("fx2").ifclk, 20.8)
except ConstraintError:
pass
def __init__(self, programmer="openocd"):
# XC6SLX45T-3FGG484C
XilinxPlatform.__init__(self, "xc6slx45t-fgg484-3", _io, _connectors)
self.programmer = programmer
pins = {
'ProgPin': 'PullUp',
'DonePin': 'PullUp',
'TckPin': 'PullNone',
'TdiPin': 'PullNone',
'TdoPin': 'PullNone',
'TmsPin': 'PullNone',
'UnusedPin': 'PullNone',
}
for pin, config in pins.items():
self.toolchain.bitgen_opt += " -g %s:%s " % (pin, config)
# FPGA AUX is connected to the 3.3V supply
self.add_platform_command("""CONFIG VCCAUX="3.3";""")
def __init__(self, programmer="openocd", vccb2_voltage="VCC3V3"):
# Some IO configurations only work at certain vccb2 voltages.
if vccb2_voltage == "VCC3V3":
_io.extend(_io_vccb2_3v3)
elif vccb2_voltage == "VCC2V5":
_io.extend(_io_vccb2_2v5)
else:
raise SystemError("Unknown vccb2_voltage=%r" % vccb2_voltage)
# Resolve the LVCMOS_BANK2 voltage level before anything uses the _io
# definition.
LVCMOS_BANK2.set(vccb2_voltage)
# XC6SLX45-2CSG324C
XilinxPlatform.__init__(self, "xc6slx45-csg324-3", _io, _connectors)
self.programmer = programmer
# FPGA AUX is connected to the 3.3V supply on the Atlys
self.add_platform_command("""CONFIG VCCAUX="3.3";""")
def __init__(self, programmer="openocd"):
# XC6SLX45T-3FGG484C
XilinxPlatform.__init__(self, "xc6slx45t-fgg484-3", _io, _connectors)
self.programmer = programmer
pins = {
'ProgPin': 'PullUp',
'DonePin': 'PullUp',
'TckPin': 'PullNone',
'TdiPin': 'PullNone',
'TdoPin': 'PullNone',
'TmsPin': 'PullNone',
'UnusedPin': 'PullNone',
}
for pin, config in pins.items():
self.toolchain.bitgen_opt += " -g %s:%s " % (pin, config)
# FPGA AUX is connected to the 3.3V supply
self.add_platform_command("""CONFIG VCCAUX="3.3";""")
def __init__(self, device, pins, std):
cs_n, clk, mosi, miso = pins[:4]
io = ["spiflash", 0,
Subsignal("cs_n", Pins(cs_n)),
Subsignal("mosi", Pins(mosi)),
Subsignal("miso", Pins(miso), Misc("PULLUP")),
IOStandard(std),
]
if clk:
io.append(Subsignal("clk", Pins(clk)))
for i, p in enumerate(pins[4:]):
io.append(Subsignal("pullup{}".format(i), Pins(p), Misc("PULLUP")))
XilinxPlatform.__init__(self, device, [io])
if isinstance(self.toolchain, XilinxVivadoToolchain):
self.toolchain.bitstream_commands.append(
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]"
)
elif isinstance(self.toolchain, XilinxISEToolchain):
self.toolchain.bitgen_opt += " -g compress"
def __init__(self, programmer="xc3sprog"):
# XC6SLX45T-3FGG484C
XilinxPlatform.__init__(self, "xc6slx45t-fgg484-3", _io, _connectors)
pins = {
"ProgPin": "PullUp",
"DonePin": "PullUp",
"TckPin": "PullNone",
"TdiPin": "PullNone",
"TdoPin": "PullNone",
"TmsPin": "PullNone",
"UnusedPin": "PullNone",
}
for pin, config in pins.items():
self.toolchain.bitgen_opt += " -g %s:%s " % (pin, config)
self.programmer = programmer
# FPGA AUX is connected to the 3.3V supply
self.add_platform_command("""CONFIG VCCAUX="3.3";""")
def __init__(self, device, pins, std):
cs_n, clk, mosi, miso = pins[:4]
io = [
"spiflash",
0,
Subsignal("cs_n", Pins(cs_n)),
Subsignal("mosi", Pins(mosi)),
Subsignal("miso", Pins(miso), Misc("PULLUP")),
IOStandard(std),
]
if clk:
io.append(Subsignal("clk", Pins(clk)))
for i, p in enumerate(pins[4:]):
io.append(Subsignal("pullup{}".format(i), Pins(p), Misc("PULLUP")))
XilinxPlatform.__init__(self, device, [io])
if isinstance(self.toolchain, XilinxVivadoToolchain):
self.toolchain.bitstream_commands.append(
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]"
)
elif isinstance(self.toolchain, XilinxISEToolchain):
self.toolchain.bitgen_opt += " -g compress"
def __init__(self, programmer="openocd"):
XilinxPlatform.__init__(self, "xc6slx45-csg324-3", _io, _connectors)
self.toolchain.bitgen_opt += " -g Compress -g ConfigRate:6"
self.programmer = programmer
def __init__(self, device="xc6slx25", programmer="openocd"):
XilinxPlatform.__init__(self, device + "-3-ftg256", _io, _connectors)
self.programmer = programmer
def __init__(self):
XilinxPlatform.__init__(self, "xc6slx45-csg324-3", _io, _connectors)
self.toolchain.bitgen_opt += " -g Compress -g ConfigRate:6"
def __init__(self, device="xc6slx25", programmer="fpgaprog"):
self.programmer = programmer
XilinxPlatform.__init__(self, device+"-3-ftg256", _io, _connectors)
def __init__(self):
XilinxPlatform.__init__(self, "xc3s200a-ft256-4", _ios, _connectors)
def __init__(self):
XilinxPlatform.__init__(self, "xc7z020-clg484-1", _io)
def __init__(self, programmer="openocd"):
XilinxPlatform.__init__(self, "xc6slx45-csg324-3", _io, _connectors)
self.toolchain.bitgen_opt += " -g Compress -g ConfigRate:6"
self.programmer = programmer
def __init__(self):
XilinxPlatform.__init__(self, "xc6slx9-2csg225", _ios, _connectors)
def __init__(self):
XilinxPlatform.__init__(self, "xc6slx150t-fgg676-3", _io)
def __init__(self):
XilinxPlatform.__init__(self, "xc5vsx95t-ff1136-1", _io)
def __init__(self):
XilinxPlatform.__init__(self, "xc3s1400a-ft256-4", _io)
self.toolchain.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g UnusedPin:PullUp"
def __init__(self):
XilinxPlatform.__init__(self, "xc6vlx240t-ff1156-1", _io)
def __init__(self):
XilinxPlatform.__init__(self, "xc6slx45-fgg484-2", _io)
self.add_platform_command("CONFIG VCCAUX=\"3.3\";\n")
def __init__(self, device="xc3s200a-4-vq100"):
XilinxPlatform.__init__(self, device, _io, _connectors)
# Small device- optimize for AREA instead of SPEED (LM32 runs at about
# 60-65MHz in AREA configuration).
self.toolchain.xst_opt = """-ifmt MIXED
def __init__(self):
XilinxPlatform.__init__(self, "xc6slx150-3csg484", _io)
self.add_platform_command("""
CONFIG VCCAUX = "2.5";
""")
def __init__(self, device="xc6slx25", programmer="openocd"):
XilinxPlatform.__init__(self, device+"-3-ftg256", _io, _connectors)
self.programmer = programmer
def __init__(self):
XilinxPlatform.__init__(self, "xc6slx45-fgg484-2", _io)
def __init__(self):
XilinxPlatform.__init__(self, "xc6slx9-csg324-2", _io, _connectors)
