def __init__(self, sdram_controller_type="minicon", **kwargs): platform = kasli.Platform() platform.toolchain.bitstream_commands.extend([ "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]", "set_property CFGBVS VCCO [current_design]", "set_property CONFIG_VOLTAGE 2.5 [current_design]", ]) SoCSDRAM.__init__(self, platform, clk_freq=125*1000000, cpu_reset_address=0x400000, **kwargs) self.submodules.crg = _CRG(platform) self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/self.clk_freq) self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) sdram_module = MT41K256M16(self.clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_controller_type, sdram_module.geom_settings, sdram_module.timing_settings) self.csr_devices.append("ddrphy") if not self.integrated_rom_size: spiflash_pads = platform.request("spiflash2x") spiflash_pads.clk = Signal() self.specials += Instance("STARTUPE2", i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0, i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1) self.submodules.spiflash = spi_flash.SpiFlash(spiflash_pads, dummy=5, div=2) self.config["SPIFLASH_PAGE_SIZE"] = 256 self.config["SPIFLASH_SECTOR_SIZE"] = 0x10000 self.flash_boot_address = 0x450000 self.register_rom(self.spiflash.bus, 16*1024*1024) self.csr_devices.append("spiflash")
def __init__(self, sdram_controller_type="minicon", hw_rev="v1.0", **kwargs): platform = kasli.Platform(hw_rev=hw_rev) SoCSDRAM.__init__(self, platform, clk_freq=125e6 * 15.25 / 16, cpu_reset_address=0x400000, **kwargs) self.submodules.crg = _CRG(platform) self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9 / self.clk_freq) self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) sdram_module = MT41K256M16(self.clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_controller_type, sdram_module.geom_settings, sdram_module.timing_settings) self.csr_devices.append("ddrphy") if not self.integrated_rom_size: spiflash_pads = platform.request("spiflash2x") spiflash_pads.clk = Signal() self.specials += Instance("STARTUPE2", i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0, i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1) self.submodules.spiflash = spi_flash.SpiFlash(spiflash_pads, dummy=5, div=2) self.config["SPIFLASH_PAGE_SIZE"] = 256 self.config["SPIFLASH_SECTOR_SIZE"] = 0x10000 self.flash_boot_address = 0x450000 self.register_rom(self.spiflash.bus, 16 * 1024 * 1024) self.csr_devices.append("spiflash")
def __init__(self, sdram_controller_type="minicon", hw_rev=None, **kwargs): if hw_rev is None: hw_rev = "v1.0" platform = kasli.Platform(hw_rev=hw_rev) platform.add_extension(virtual_platform._io) SoCSDRAM.__init__(self, platform, clk_freq=125e6 * 14.5 / 16, cpu_reset_address=0x400000, **kwargs) self.remove_subsystem_by_type("MOR1KX") self.submodules.cpu = bridge_cpu = BridgeCPU(platform=platform) self.add_wb_master(bridge_cpu.dbus) self.config["HW_REV"] = hw_rev self.submodules.crg = _KasliCRG(platform) self.submodules.ddrphy = BridgeDFI( pads=self.platform.request("virt_ddr")) sdram_module = MT48LC4M16(self.clk_freq, "1:1") self.register_sdram(self.ddrphy, sdram_controller_type, sdram_module.geom_settings, sdram_module.timing_settings) self.csr_devices.append("ddrphy") if not self.integrated_rom_size: spiflash_pads = self.platform.request("virt_spiflash") spiflash_dummy_clks = 3 self.submodules.spiflash = spi_flash.SpiFlash( spiflash_pads, dummy=spiflash_dummy_clks, div=2) self.config["SPIFLASH_DUMMY_CLKS"] = spiflash_dummy_clks self.config["SPIFLASH_PAGE_SIZE"] = 256 self.config["SPIFLASH_SECTOR_SIZE"] = 0x10000 self.flash_boot_address = 0xb40000 self.register_rom(self.spiflash.bus, 16 * 1024 * 1024) self.csr_devices.append("spiflash")
class Top(Module): def __init__(self, platform): self.submodules += Microscope(platform.request("serial"), 1/16e-9) self.submodules += CRG(platform) deserializer = Deserializer(platform.request("camera_link_in")) self.submodules += deserializer self.submodules += [ add_probe_async("grabber", "q_clk", deserializer.q_clk), add_probe_buffer("grabber", "q", deserializer.q, clock_domain="cl") ] if __name__ == "__main__": from migen.build.platforms.sinara import kasli plat = kasli.Platform(hw_rev="v1.1") plat.add_extension([ ("camera_link_in", 0, Subsignal("clk_p", Pins("eem6:d0_cc_p")), Subsignal("clk_n", Pins("eem6:d0_cc_n")), Subsignal("sdi_p", Pins("eem6:d1_p eem6:d2_p eem6:d3_p eem6:d4_p")), Subsignal("sdi_n", Pins("eem6:d1_n eem6:d2_n eem6:d3_n eem6:d4_n")), IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE") ), ]) top = Top(plat) plat.build(top)