def __init__(self, hw_rev="v1.0"):
if hw_rev == "v1.0":
io_rev = _io_v1_0
elif hw_rev == "v1.1":
io_rev = _io_v1_1
else:
raise ValueError("Unknown hardware revision", hw_rev)
XilinxPlatform.__init__(
self, "xc7a100t-fgg484-2", _io_common + io_rev, _connectors,
toolchain="vivado")
self.add_platform_command(
"set_property INTERNAL_VREF 0.750 [get_iobanks 35]")
self.toolchain.bitstream_commands.extend([
# NOTE: disable this on Kasli/v1.0 boards where the XADC reference
# has not been fixed.
"set_property BITSTREAM.CONFIG.OVERTEMPPOWERDOWN Enable [current_design]",
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
"set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]",
"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 2 [current_design]",
"set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]",
"set_property BITSTREAM.CONFIG.USERID \"{:#010x}\" [current_design]".format(self.userid),
"set_property CFGBVS VCCO [current_design]",
"set_property CONFIG_VOLTAGE 2.5 [current_design]",
])
def __init__(self):
XilinxPlatform.__init__(self, "xc6slx9-2csg324", _io)
self.add_platform_command("""
CONFIG VCCAUX = "3.3";
""")
self.toolchain.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g SPI_buswidth:4"
self.toolchain.ise_commands = """
def __init__(self):
XilinxPlatform.__init__(self, "xc7a15t-csg325-1", _io, toolchain="vivado")
self.toolchain.bitstream_commands.extend([
# FIXME: enable this when the XADC reference wiring is fixed
# "set_property BITSTREAM.CONFIG.OVERTEMPPOWERDOWN Enable [current_design]",
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
"set_property CFGBVS VCCO [current_design]",
"set_property CONFIG_VOLTAGE 3.3 [current_design]",
])
def __init__(self, toolchain="vivado", programmer="xc3sprog"):
XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors,
toolchain=toolchain)
if toolchain == "ise":
self.toolchain.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g ConfigRate:12 -g SPI_buswidth:4"
elif toolchain == "vivado":
self.toolchain.bitstream_commands = ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
self.programmer = programmer
def __init__(self, toolchain="vivado", programmer="vivado"):
XilinxPlatform.__init__(self, "xc7a35ticsg324-1L", _io, _connectors,
toolchain=toolchain)
self.toolchain.bitstream_commands = \
["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = \
["write_cfgmem -force -format bin -interface spix4 -size 16 "
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
self.programmer = programmer
self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 34]")
def __init__(self):
XilinxPlatform.__init__(self, "xc3s500e-4pq208", _io)
self.toolchain.xst_opt = """-ifmt MIXED
-bram_utilization_ratio -1
-opt_level 2
-opt_mode SPEED
-register_balancing yes"""
self.toolchain.bitgen_opt += (" -g GTS_cycle:3 -g LCK_cycle:4 "
"-g GWE_cycle:5 -g DONE_cycle:6")
self.toolchain.ise_commands += """
def __init__(self, larger=False):
chip = "xc7a50t-csg325-3" if larger else "xc7a35t-csg325-3"
XilinxPlatform.__init__(self, chip, _io,
toolchain="vivado", name="sayma_rtm")
self.toolchain.bitstream_commands.extend([
"set_property BITSTREAM.CONFIG.OVERTEMPPOWERDOWN Enable [current_design]",
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
"set_property CFGBVS VCCO [current_design]",
"set_property CONFIG_VOLTAGE 3.3 [current_design]",
])
def __init__(self):
XilinxPlatform.__init__(
self, "xcku040-ffva1156-1-c", _io, _connectors,
toolchain="vivado")
self.toolchain.bitstream_commands.extend([
# FIXME: enable this when the XADC reference wiring is fixed
# "set_property BITSTREAM.CONFIG.OVERTEMPPOWERDOWN Enable [current_design]",
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
"set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]",
"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
"set_property CFGBVS VCCO [current_design]",
"set_property CONFIG_VOLTAGE 3.3 [current_design]",
])
def __init__(self):
XilinxPlatform.__init__(self, "xcku040-ffva1156-2-e", _io, _connectors,
toolchain="vivado")
def __init__(self, device="xc6slx9", programmer="xc3sprog"):
self.programmer = programmer
XilinxPlatform.__init__(self, device+"-3-ftg256", _io, _connectors)
def __init__(self):
XilinxPlatform.__init__(self, "xc6vlx240t-ff1156-1", _io)
def __init__(self):
XilinxPlatform.__init__(self, "xc6slx45-fgg484-2", _io)
def __init__(self):
XilinxPlatform.__init__(self, "xcku040-ffva1156-1-c", _io, toolchain="vivado")
def __init__(self):
XilinxPlatform.__init__(self, "xc6slx150-3csg484", _io)
self.add_platform_command("""
CONFIG VCCAUX = "2.5";
""")
def __init__(self):
XilinxPlatform.__init__(self, "xc7a15t-csg325-1", _io, toolchain="vivado")
def __init__(self):
XilinxPlatform.__init__(self, "xc6slx9-tqg144-3", _io)
def __init__(self):
XilinxPlatform.__init__(
self, "xc7a100t-fgg484-2", _io, _connectors,
toolchain="vivado")
self.add_platform_command(
"set_property INTERNAL_VREF 0.750 [get_iobanks 35]")
def __init__(self, device="xc3s200a-4-vq100"):
XilinxPlatform.__init__(self, device, _io, _connectors)
# Small device- optimize for AREA instead of SPEED (LM32 runs at about
# 60-65MHz in AREA configuration).
self.toolchain.xst_opt = """-ifmt MIXED
def __init__(self):
XilinxPlatform.__init__(self, "xc3s200a-ft256-4", _ios, _connectors)
def __init__(self):
XilinxPlatform.__init__(self, "xc6slx9-tqg144-2", _io, _connectors)
def __init__(self):
XilinxPlatform.__init__(self, "xc5vsx95t-ff1136-1", _io)
def __init__(self):
XilinxPlatform.__init__(self, "xc6slx16-ftg256", _io, _connectors)
def __init__(self):
XilinxPlatform.__init__(self,
"xc7z045-ffg900-1",
_io,
toolchain="vivado")
def __init__(self):
XilinxPlatform.__init__(self, "xc6slx45-fgg484-2", _io)
def __init__(self):
XilinxPlatform.__init__(self, "xc6slx16-ftg256", _io, _connectors)
def __init__(self):
XilinxPlatform.__init__(self, "xc6slx16-csg324", _io, _connectors)
def __init__(self):
XilinxPlatform.__init__(self, "xc6slx45-csg324-3", _io, _connectors)
self.toolchain.bitgen_opt += " -g Compress -g ConfigRate:6"
def __init__(self):
XilinxPlatform.__init__(self, "xc6slx9-2csg225", _ios, _connectors)
def __init__(self):
XilinxPlatform.__init__(self, "xc7z020-clg484-1", _io)
def __init__(self):
XilinxPlatform.__init__(self, "xc2c128-6-tq144", _io)
self.toolchain.xst_opt = "-ifmt MIXED"
self.toolchain.par_opt = ("-optimize speed -unused pullup "
"-iostd LVCMOS33")
def __init__(self):
XilinxPlatform.__init__(self, "xc6slx150t-fgg676-3", _io)
def __init__(self):
XilinxPlatform.__init__(self, "xc3s1400a-ft256-4", _io)
self.toolchain.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g UnusedPin:PullUp"
def __init__(self):
XilinxPlatform.__init__(self, "xc6slx45-fgg484-2", _io)
self.add_platform_command("CONFIG VCCAUX=\"3.3\";\n")
def __init__(self):
XilinxPlatform.__init__(
self, "xcku040-ffva1156-1-c", _io, _connectors,
toolchain="vivado")
