def __init__(self, *args, ethmac_nrxslots=2, ethmac_ntxslots=2, **kwargs):
BaseSoC.__init__(self, *args, **kwargs)
self.csr_devices += ["ethphy", "ethmac"]
self.interrupt_devices.append("ethmac")
eth_clocks = self.platform.request("eth_clocks")
self.submodules.ethphy = LiteEthPHY(eth_clocks,
self.platform.request("eth"),
clk_freq=self.clk_freq)
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy,
dw=32,
interface="wishbone",
nrxslots=ethmac_nrxslots,
ntxslots=ethmac_ntxslots)
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac",
self.mem_map["ethmac"] | self.shadow_base,
(ethmac_nrxslots + ethmac_ntxslots) * 0x800)
self.crg.cd_sys.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
# period constraints are required here because of vivado
self.platform.add_period_constraint(self.crg.cd_sys.clk, 8.0)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.0)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_tx.clk,
eth_clocks.rx)
def __init__(self, *args, ethmac_nrxslots=2, ethmac_ntxslots=2, **kwargs):
BaseSoC.__init__(self, *args, **kwargs)
self.create_qpll()
self.csr_devices += ["ethphy", "ethmac"]
self.interrupt_devices.append("ethmac")
self.submodules.ethphy = A7_1000BASEX(
self.ethphy_qpll_channel, self.platform.request("mgt113", 3),
self.clk_freq)
self.platform.add_period_constraint(self.ethphy.txoutclk, 16.)
self.platform.add_period_constraint(self.ethphy.rxoutclk, 16.)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.ethphy.txoutclk,
self.ethphy.rxoutclk)
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy,
dw=self.cpu_dw,
interface="wishbone",
endianness=self.cpu.endianness,
nrxslots=2,
ntxslots=2)
ethmac_len = (ethmac_nrxslots + ethmac_ntxslots) * 0x800
self.add_wb_slave(self.mem_map["ethmac"], ethmac_len, self.ethmac.bus)
self.add_memory_region("ethmac",
self.mem_map["ethmac"] | self.shadow_base,
ethmac_len)
def __init__(self, *args, ethmac_nrxslots=2, ethmac_ntxslots=2, **kwargs):
BaseSoC.__init__(self, *args, **kwargs)
self.csr_devices += ["ethphy", "ethmac"]
self.interrupt_devices.append("ethmac")
self.comb += self.platform.request("sfp_tx_disable", 0).eq(0)
self.submodules.ethphy = KU_1000BASEX(
self.platform.request("gth_clk200"),
self.platform.request("sfp", 0),
self.clk_freq)
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone",
nrxslots=ethmac_nrxslots, ntxslots=ethmac_ntxslots)
ethmac_len = (ethmac_nrxslots + ethmac_ntxslots) * 0x800
self.add_wb_slave(self.mem_map["ethmac"], ethmac_len, self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base,
ethmac_len)
self.crg.cd_sys.clk.attr.add("keep")
self.ethphy.cd_eth_rx.clk.attr.add("keep")
self.ethphy.cd_eth_tx.clk.attr.add("keep")
self.platform.add_period_constraint(self.ethphy.cd_eth_rx.clk, 1e9/125e6)
self.platform.add_period_constraint(self.ethphy.cd_eth_tx.clk, 1e9/125e6)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.ethphy.cd_eth_rx.clk,
self.ethphy.cd_eth_tx.clk)
def __init__(self, *args, ethmac_nrxslots=2, ethmac_ntxslots=2, **kwargs):
BaseSoC.__init__(self, *args, **kwargs)
self.csr_devices += ["ethphy", "ethmac"]
self.interrupt_devices.append("ethmac")
eth_clocks = self.platform.request("eth_clocks")
eth = self.platform.request("eth_mii")
self.submodules.ethphy = LiteEthPHY(eth_clocks,
eth, clk_freq=self.clk_freq)
self.comb += eth.mdc.eq(0)
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone",
nrxslots=ethmac_nrxslots, ntxslots=ethmac_ntxslots)
ethmac_len = (ethmac_nrxslots + ethmac_ntxslots) * 0x800
self.add_wb_slave(self.mem_map["ethmac"], ethmac_len, self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base,
ethmac_len)
self.platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets eth_clocks_tx_IBUF_inst/O]")
self.platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets eth_clocks_rx_IBUF_inst/O]")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 40.0)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 40.0)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_tx.clk, self.ethphy.crg.cd_eth_rx.clk)
def __init__(self, *args, ethmac_nrxslots=2, ethmac_ntxslots=2, **kwargs):
BaseSoC.__init__(self, *args, **kwargs)
self.create_qpll()
self.csr_devices += ["ethphy", "ethmac"]
self.interrupt_devices.append("ethmac")
sfp = self.platform.request("sfp", 0)
self.submodules.ethphy = A7_1000BASEX(self.ethphy_qpll_channel, sfp, self.clk_freq)
self.platform.add_period_constraint(self.ethphy.txoutclk, 16.)
self.platform.add_period_constraint(self.ethphy.rxoutclk, 16.)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.ethphy.txoutclk, self.ethphy.rxoutclk)
sfp_ctl = self.platform.request("sfp_ctl", 0)
self.comb += [
sfp_ctl.rate_select.eq(0),
sfp_ctl.tx_disable.eq(0),
sfp_ctl.led.eq(~sfp_ctl.los & ~sfp_ctl.tx_fault & sfp_ctl.mod_present &
self.ethphy.link_up),
]
self.submodules.ethmac = LiteEthMAC(
phy=self.ethphy, dw=32, interface="wishbone",
nrxslots=ethmac_nrxslots, ntxslots=ethmac_ntxslots)
ethmac_len = (ethmac_nrxslots + ethmac_ntxslots) * 0x800
self.add_wb_slave(self.mem_map["ethmac"], ethmac_len, self.ethmac.bus)
self.add_memory_region("ethmac",
self.mem_map["ethmac"] | self.shadow_base, ethmac_len)
def __init__(self, ethmac_nrxslots=2, ethmac_ntxslots=2, **kwargs):
BaseSoC.__init__(self, **kwargs)
self.submodules.ethphy = AfckPCSPMA(
platform=self.platform,
clk_pads=self.platform.request("mgt116_clk1"),
data_pads=self.platform.request("mgt116", 3),
sys_clk_freq=125e6,
cd_idelayctrl="clk200")
self.submodules.ethmac = LiteEthMAC(
phy=self.ethphy,
dw=32,
interface="wishbone",
nrxslots=2,
ntxslots=2)
ethmac_len = (ethmac_nrxslots + ethmac_ntxslots) * 0x800
self.add_wb_slave(self.mem_map["ethmac"], ethmac_len, self.ethmac.bus)
self.add_memory_region("ethmac",
self.mem_map["ethmac"] | self.shadow_base, ethmac_len)
self.csr_devices += ["ethmac"]
self.interrupt_devices.append("ethmac")
self.platform.add_period_constraint(self.ethphy.cd_eth_rx.clk, 1e9 / 125e6)
self.platform.add_period_constraint(self.ethphy.cd_eth_tx.clk, 1e9 / 125e6)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.ethphy.cd_eth_rx.clk,
self.ethphy.cd_eth_tx.clk)
def __init__(self, *args, **kwargs):
BaseSoC.__init__(self, *args, **kwargs)
platform = self.platform
if platform.name == "mixxeo":
self.submodules.leds = gpio.GPIOOut(platform.request("user_led"))
self.csr_devices.append("leds")
if platform.name == "m1":
self.submodules.buttons = gpio.GPIOIn(
Cat(platform.request("user_btn", 0),
platform.request("user_btn", 2)))
self.submodules.leds = gpio.GPIOOut(
Cat(platform.request("user_led", i) for i in range(2)))
self.csr_devices += ["buttons", "leds"]
self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"),
platform.request("eth"))
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy,
dw=32,
interface="wishbone")
self.add_wb_slave(self.mem_map["ethmac"], 0x2000, self.ethmac.bus)
self.add_memory_region("ethmac",
self.mem_map["ethmac"] | self.shadow_base,
0x2000)
self.csr_devices += ["ethphy", "ethmac"]
self.interrupt_devices.append("ethmac")
def __init__(self,
*args,
ethmac_nrxslots=2,
ethmac_ntxslots=2,
ethphy_qpll_channel=None,
**kwargs):
BaseSoC.__init__(self, *args, **kwargs)
self.csr_devices += ["ethphy", "ethmac"]
self.interrupt_devices.append("ethmac")
sfp = self.platform.request("sfp", 0)
self.comb += [
sfp.rate_select.eq(1),
sfp.tx_disable.eq(0),
]
if ethphy_qpll_channel is None:
clk125 = self.platform.request("clk125_gtp")
clk125_buf = Signal()
self.specials += Instance("IBUFDS_GTE2",
i_CEB=0,
i_I=clk125.p,
i_IB=clk125.n,
o_O=clk125_buf)
qpll_settings = QPLLSettings(refclksel=0b001,
fbdiv=4,
fbdiv_45=5,
refclk_div=1)
qpll = QPLL(clk125_buf, qpll_settings)
self.submodules += qpll
ethphy_qpll_channel = qpll.channels[0]
sfp = self.platform.request("sfp_gtp", 0)
self.submodules.ethphy = A7_1000BASEX(ethphy_qpll_channel, sfp,
self.clk_freq)
self.platform.add_period_constraint(self.ethphy.txoutclk, 16e-9)
self.platform.add_period_constraint(self.ethphy.rxoutclk, 16e-9)
self.platform.add_period_constraint(self.crg.cd_sys.clk, self.clk_freq)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.ethphy.txoutclk,
self.ethphy.rxoutclk)
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy,
dw=32,
interface="wishbone",
nrxslots=ethmac_nrxslots,
ntxslots=ethmac_ntxslots)
ethmac_len = (ethmac_nrxslots + ethmac_ntxslots) * 0x800
self.add_wb_slave(self.mem_map["ethmac"], ethmac_len, self.ethmac.bus)
self.add_memory_region("ethmac",
self.mem_map["ethmac"] | self.shadow_base,
ethmac_len)
def __init__(self, platform, **kwargs):
BaseSoC.__init__(self, platform, **kwargs)
self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"),
platform.request("eth"))
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy,
dw=32,
interface="wishbone",
with_preamble_crc=False)
self.add_wb_slave(self.mem_map["ethmac"], 0x2000, self.ethmac.bus)
self.add_memory_region("ethmac",
self.mem_map["ethmac"] | self.shadow_base,
0x2000)
self.csr_devices += ["ethphy", "ethmac"]
self.interrupt_devices.append("ethmac")
def __init__(self, *args, ethmac_nrxslots=2, ethmac_ntxslots=2, **kwargs):
BaseSoC.__init__(self, *args, **kwargs)
self.submodules.ethcrg = _EthernetCRG(self.platform, self.crg.cd_sys)
self.csr_devices += ["ethphy", "ethmac"]
self.interrupt_devices.append("ethmac")
eth = self.platform.request("eth")
self.submodules.ethphy = LiteEthPHYRGMII(eth)
self.comb += eth.mdc.eq(0)
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone",
nrxslots=ethmac_nrxslots, ntxslots=ethmac_ntxslots)
ethmac_len = (ethmac_nrxslots + ethmac_ntxslots) * 0x800
self.add_wb_slave(self.mem_map["ethmac"], ethmac_len, self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base,
ethmac_len)
def __init__(self, *args, ethmac_nrxslots=2, ethmac_ntxslots=2, **kwargs):
VirtualBaseSoC.__init__(self,
cpu_type="or1k",
sdram_controller_type="minicon",
l2_size=1024 * 16,
integrated_sram_size=8192,
**kwargs)
self.csr_devices += ["ethmac", "ethphy"]
self.interrupt_devices.append("ethmac")
# TODO: add pads
ethphy = LiteEthPHYModel(pads=self.platform.request("model_eth"))
self.submodules.ethphy = ethphy
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy,
dw=32,
interface="wishbone",
nrxslots=ethmac_nrxslots,
ntxslots=ethmac_ntxslots)
ethmac_len = (ethmac_nrxslots + ethmac_ntxslots) * 0x800
self.add_wb_slave(self.mem_map["ethmac"], ethmac_len, self.ethmac.bus)
self.add_memory_region("ethmac",
self.mem_map["ethmac"] | self.shadow_base,
ethmac_len)
def __init__(self, *args, ethmac_nrxslots=2, ethmac_ntxslots=2, **kwargs):
BaseSoC.__init__(self, *args, **kwargs)
self.csr_devices += ["ethphy", "ethmac"]
self.interrupt_devices.append("ethmac")
eth_clocks = self.platform.request("eth_clocks")
self.submodules.ethphy = LiteEthPHY(eth_clocks,
self.platform.request("eth"),
clk_freq=self.clk_freq)
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy,
dw=32,
interface="wishbone",
nrxslots=ethmac_nrxslots,
ntxslots=ethmac_ntxslots)
ethmac_len = (ethmac_nrxslots + ethmac_ntxslots) * 0x800
self.add_wb_slave(self.mem_map["ethmac"], ethmac_len, self.ethmac.bus)
self.add_memory_region("ethmac",
self.mem_map["ethmac"] | self.shadow_base,
ethmac_len)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_tx.clk,
eth_clocks.rx)