def __init__(self, toolchain="vivado", sdram_controller_type="minicon", **kwargs):
platform = kc705.Platform(toolchain=toolchain)
SoCSDRAM.__init__(self, platform,
clk_freq=125*1000000, cpu_reset_address=0xaf0000,
**kwargs)
self.csr_devices += ["spiflash", "ddrphy"]
self.submodules.crg = _CRG(platform)
self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"))
sdram_module = MT8JTF12864(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy, sdram_controller_type,
sdram_module.geom_settings, sdram_module.timing_settings)
if not self.integrated_rom_size:
spiflash_pads = platform.request("spiflash")
spiflash_pads.clk = Signal()
self.specials += Instance("STARTUPE2",
i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0,
i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1)
self.submodules.spiflash = spi_flash.SpiFlash(spiflash_pads, dummy=11, div=2)
self.config["SPIFLASH_PAGE_SIZE"] = 256
self.config["SPIFLASH_SECTOR_SIZE"] = 0x10000
self.flash_boot_address = 0xb00000
self.register_rom(self.spiflash.bus, 16*1024*1024)
def __init__(self, sdram_controller_type="minicon", crg=None, integrated_rom_size=0, **kwargs):
platform = afck1v1.Platform()
SoCSDRAM.__init__(self,
platform = platform,
clk_freq = 125000000,
integrated_rom_size = integrated_rom_size,
cpu_reset_address = 0x000000 if integrated_rom_size else 0xaf0000,
**kwargs)
if crg is None:
self.submodules.crg = _CRG(platform)
else:
self.submodules.crg = crg(platform)
# sdram
self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"))
sdram_module = MT41K512M8(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_controller_type,
sdram_module.geom_settings,
sdram_module.timing_settings)
self.csr_devices.append("ddrphy")
self.flash_boot_address = 0xb40000
if not self.integrated_rom_size:
spiflash_pads = platform.request("spiflash")
spiflash_pads.clk = Signal()
self.specials += Instance("STARTUPE2",
i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0,
i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1)
self.comb += platform.request("spiflash_fcsb").eq(1)
self.submodules.spiflash = spi_flash.SpiFlashSingle(spiflash_pads, dummy=8, div=4,
endianness="little" if self.cpu_type == "vexriscv" else "big")
self.config["SPIFLASH_PAGE_SIZE"] = 256
self.config["SPIFLASH_SECTOR_SIZE"] = 0x10000
self.flash_boot_address = 0xb40000
self.register_rom(self.spiflash.bus, 16*1024*1024)
self.csr_devices.append("spiflash")