def __init__(self, axi4_bus):
if isinstance(axi4_bus, basestring):
# create axi4lite bus from given device path
self.axi4_bus = AXI4LiteBus(axi4_bus, MIXLTC2386SGDef.REG_SIZE)
else:
self.axi4_bus = axi4_bus
self._data_deal = DataOperate()
def __init__(self, axi4_bus):
if isinstance(axi4_bus, basestring):
# create axi4lite bus from given device path
self.axi4_bus = AXI4LiteBus(axi4_bus, MIXDMM101SGRDef.REG_SIZE)
else:
self.axi4_bus = axi4_bus
self._data_deal = DataOperate()
self.signal_meter = None
self.sample_rate = MIXDMM101SGRDef.FREQ_MAX
self.enable()
def __init__(self, axi4_bus=None):
if axi4_bus is None:
self.axi4_bus = AXI4LiteBusEmulator(
"mix_axilitetostream_sg_emulator", MIXAxiLiteToStreamSGDef.REGISTER_SIZE)
elif isinstance(axi4_bus, basestring):
# device path passed in; create axi4litebus here.
self.axi4_bus = AXI4LiteBus(axi4_bus, MIXAxiLiteToStreamSGDef.REGISTER_SIZE)
else:
self.axi4_bus = axi4_bus
self.__data_deal = DataOperate()
def enable_continuous_sampling(self, over_sampling, adc_range,
sampling_rate):
'''
AD760X enable continuous measure, there is an improvement in SNR as
over_sampling increases. Refer to AD7608 Datasheet Table 8(Page26).
Args:
over_sampling: int, [0~7], OS[2:0] oversample bit value.
adc_range: string, ['10V', '5V'], reference voltage range.
sampling_rate: int, [2000~200000], sampling_rate.
Examples:
ad760x.enable_continuous_sampling(0, '10V', 2000)
'''
assert 0 <= over_sampling < 8
assert adc_range in ['10V', '5V']
assert isinstance(sampling_rate,
int) and 2000 <= sampling_rate <= 200000
# Set continuos mode, set OS bit, select range
rd_data = self.axi4_bus.read_8bit_inc(MIXAd760xSGDef.ENABLE_REG, 2)
rd_data[0] = (0x1 << MIXAd760xSGDef.ENABLE_BIT)
rd_data[0] |= (0x1 << MIXAd760xSGDef.CONTINUOUS_MODE_BIT)
rd_data[1] = (rd_data[1] & 0xF0) | (
MIXAd760xSGDef.RANGE_CONFIG[adc_range] | over_sampling)
self.axi4_bus.write_8bit_inc(MIXAd760xSGDef.ENABLE_REG, rd_data)
# configure sample rate
wr_data = DataOperate.int_2_list(
int((AXI4Def.AXI4_CLOCK / sampling_rate) - 2), 2)
self.axi4_bus.write_8bit_inc(MIXAd760xSGDef.SAMPLE_RATE_REG, wr_data)
# start sample
self.axi4_bus.write_8bit_inc(MIXAd760xSGDef.SAMPLE_START_REG, [0x01])
def set_speed(self, speed):
'''
set the clock speed.
Args:
speed: int, [2000~12500000], unit Hz, swd transmit speed.
Examples:
# set swd clock speed as 500KHz
swd.set_speed(500000)
'''
assert MIXSWDSGDef.SPEED_MIN <= speed
assert speed <= MIXSWDSGDef.SPEED_MAX
# the BASE_CLK_FREQ register is 24 bit width.
rd_data = self.axi4_bus.read_8bit_inc(MIXSWDSGDef.BASE_CLK_FREQ_REG, 3)
# KHz to Hz.
base_clk_freq = DataOperate.list_2_int(rd_data) * 1000
# calculate the frequency division
swd_freq_div = int(((base_clk_freq) / (speed * 2)) - 2)
if swd_freq_div < 0:
swd_freq_div = 0
self.axi4_bus.write_16bit_fix(MIXSWDSGDef.SWD_CLK_DIV_REG,
[swd_freq_div])
return "done"
def __init__(self, axi4_bus=None):
if axi4_bus is None:
self.axi4_bus = AXI4LiteBusEmulator(
"pl_spi_dac_emulator", PLSPIDACDef.REG_SIZE)
elif isinstance(axi4_bus, basestring):
# device path passed in; create axi4litebus here.
self.axi4_bus = AXI4LiteBus(axi4_bus, PLSPIDACDef.REG_SIZE)
else:
self.axi4_bus = axi4_bus
self.dev_name = self.axi4_bus._dev_name
self.reg_num = 256
self.axi4_clk_frequency = 125000000
self.data_deal = DataOperate()
self.sclk_frequency = 10000000
self.open()
def enable_upload(self,
sample_rate=192000,
upload_state="off",
measure_time=0xFFFFFFFF):
'''
enable the solaris adc upload
Args:
sample_rate: int, unit Hz, default 192000, set the sample rate for adcHz.
upload_state: string, ["on", "off"], default "off".
measure_time: int, default 0xFFFFFFFF.
Returns:
string, "done", api execution successful.
Examples:
solaris.enable_upload()
'''
assert upload_state in ("on", "off")
self.gpio.set_pin(SolarisDef.LTC2378_IPCORE_GPIO,
SolarisDef.LTC2378_RMS)
self.dma.reset_channel(self.dma_channel["rms"])
self.dma.disable_channel(self.dma_channel["rms"])
if upload_state == 'on':
self.dma.enable_channel(self.dma_channel["rms"])
wr_data = DataOperate.int_2_list(measure_time & 0xFFFF, 2)
self.ipcore.meter.axi4_bus.write_8bit_inc(
SolarisDef.PL_SIGNAL_METER_MEASURE_TIME_LOW_ADDR, wr_data)
wr_data = DataOperate.int_2_list((measure_time >> 16) & 0xFFFF, 2)
self.ipcore.meter.axi4_bus.write_8bit_inc(
SolarisDef.PL_SIGNAL_METER_MEASURE_TIME_HIGH_ADDR, wr_data)
self.ipcore.spi_adc.open()
self.ipcore.spi_adc.set_sample_rate(sample_rate)
self.ipcore.meter.axi4_bus.write_8bit_inc(
SolarisDef.PL_SIGNAL_METER_MODULE_ENABLE_ADDR, [0xFE])
self.ipcore.meter.axi4_bus.write_8bit_inc(
SolarisDef.PL_SIGNAL_METER_MODULE_ENABLE_ADDR, [0xFF])
# enable the [0]: 1—Generate a Signal measure start signal, active-1, automatic reset.
self.ipcore.meter.axi4_bus.write_8bit_inc(
SolarisDef.PL_SIGNAL_METER_MEASURE_CTRL_ADDR, [0x01])
return 'done'
def set_read_ramend_addr(self, address):
'''
Set the end address for cyclic READ RAM.
Args:
address: int, the end address for cyclic READ RAM.
'''
wr_data = DataOperate.int_2_list(int(address), 2)
self.axi4_bus.write_8bit_inc(MIXRamSignalSGDef.READ_END_ADDR_REGISTER,
wr_data)
def set_continu_sample_time(self, time):
'''
Set spi sclk.
Args:
time:int, unit ms,sample time.
Examples:
ad9224r.set_continu_sample_time(1000)
'''
cnt_ns = int(time * pow(10, 6) / 8)
wr_data = DataOperate.int_2_list(cnt_ns, 4)
self.axi4_bus.write_8bit_inc(MIXADS9224RSGDef.SAMPLE_TIME_REGISTER,
wr_data)
def set_sample_rate(self, sample_rate):
'''
Set the ADS9224R chip sampling rate
Args:
sample_rate:int,[0-1500000],sampling rate.
Examples:
ad9224r.set_sample_rate(1500000)
'''
sample_fre = int(pow(10, 9) / (sample_rate * 8))
wr_data = DataOperate.int_2_list(sample_fre, 3)
self.axi4_bus.write_8bit_inc(MIXADS9224RSGDef.SAMPLE_SET_REGISTER,
wr_data)
def set_spi_sclk(self, fre_ctrl):
'''
Set spi sclk.
Args:
fre_ctrl:int, spi clock frequency.
Examples:
ad9224r.set_spi_sclk(20000000)
'''
sclk_fre = int(fre_ctrl * pow(2, 32) / self.clk_frequency)
wr_data = DataOperate.int_2_list(sclk_fre, 4)
self.axi4_bus.write_8bit_inc(MIXADS9224RSGDef.SCLK_SET_REGISTER,
wr_data)
def write_register(self, reg_addr, reg_data, conti_mode=False):
'''
MIXAD717XSG write the register value
Args:
reg_addr: hexmial, [0x00~0x3F].
reg_data: int.
Raises:
keyError: raises an MIXAD717XSGException
Examples:
ad717x.write_register(0x10, 30)
'''
assert isinstance(reg_addr, int) and isinstance(
reg_data, int) and 0 <= reg_addr <= 0x3F
if reg_addr in [0x00, 0x03, 0x04]:
raise MIXAD717XSGException("The register address is read only!")
rd_data = self.axi4_bus.read_8bit_inc(
MIXAD717XSGDef.BUSY_STAT_REGISTER, 1)
if rd_data[0] & 0x01 == 0x00:
raise MIXAD717XSGException('MIXAD717XSG Bus is busy now')
wr_data = DataOperate.int_2_list(reg_data, 4)
wr_data.append(0x3F & reg_addr)
wr_data.append(0x01)
self.axi4_bus.write_8bit_inc(MIXAD717XSGDef.WRITE_DATA_REGISTER,
wr_data)
if conti_mode is True:
return True
rd_data = [0x00]
last_time = time.time()
while (rd_data[0] & 0x01 == 0x00) and (time.time() - last_time <
AD717XDef.DEFAULT_TIMEOUT):
time.sleep(AD717XDef.DEFAULT_DELAY)
rd_data = self.axi4_bus.read_8bit_inc(
MIXAD717XSGDef.BUSY_STAT_REGISTER, 1)
if time.time() - last_time >= AD717XDef.DEFAULT_TIMEOUT:
raise MIXAD717XSGException(
'MIXAD717XSG write register wait timeout')
return True
def write_register(self, reg_addr, reg_data):
'''
AD717X write the register value
:param reg_addr: hex(0x00~0x3F)
:param reg_data: int
:raises keyError: raises an AD717XException
:example:
ad717x.write_register(0x10, 30)
'''
assert isinstance(reg_addr, int) and isinstance(reg_data, int)
assert reg_addr in AD717XDef.REGISTOR_LEN
if reg_addr in [0x00, 0x03, 0x04]:
raise AD717XException("The register address is read only!")
com_data = [(0x3F & reg_addr)]
reg_len = AD717XDef.REGISTOR_LEN[reg_addr & 0x3f]
data = DataOperate.int_2_list(reg_data, reg_len)
data.reverse()
wr_data = com_data + data
self.spi.write(wr_data)
def single_sampling(self, over_sampling, adc_range):
'''
AD760X measure single voltage, there is an improvement in SNR as
over_sampling increases. Refer to AD7608 Datasheet Table 8(Page26).
Conversion Control:
Simultaneous Sampling on All Analog Input Channels
+-------------------+-------------------+------+
| over_sampling |sampling_rate limit| unit |
+===================+===================+======+
| 0 (No OS) | 2000~200000 | 'Hz' |
+-------------------+-------------------+------+
| 1 | 2000~100000 | 'Hz' |
+-------------------+-------------------+------+
| 2 | 2000~50000 | 'Hz' |
+-------------------+-------------------+------+
| 3 | 2000~25000 | 'Hz' |
+-------------------+-------------------+------+
| 4 | 2000~12500 | 'Hz' |
+-------------------+-------------------+------+
| 5 | 2000~6250 | 'Hz' |
+-------------------+-------------------+------+
| 6 | 2000~3125 | 'Hz' |
+-------------------+-------------------+------+
| 7 (Invalid) | / | / |
+-------------------+-------------------+------+
Args:
over_sampling: int, [0~7], OS[2:0] oversample bit value.
adc_range: string, ['10V', '5V'], adc reference voltage range.
Examples:
ad760x.single_sampling(0, '10V')
'''
assert 0 <= over_sampling < 8
assert adc_range in ['10V', '5V']
# Enable and Clear Continuous mode, Set OS bit, select range
rd_data = self.axi4_bus.read_8bit_inc(MIXAd760xSGDef.ENABLE_REG, 2)
rd_data[0] = (0x1 << MIXAd760xSGDef.ENABLE_BIT)
rd_data[0] &= ~(0x1 << MIXAd760xSGDef.CONTINUOUS_MODE_BIT)
rd_data[1] = (rd_data[1] & 0xF0) | (
MIXAd760xSGDef.RANGE_CONFIG[adc_range] | over_sampling)
self.axi4_bus.write_8bit_inc(MIXAd760xSGDef.ENABLE_REG, rd_data)
# start sample
self.axi4_bus.write_8bit_inc(MIXAd760xSGDef.SAMPLE_START_REG, [0x01])
reg_data = 0
last_time = time.time()
while(reg_data & 0x01 == 0x00) and \
(time.time() - last_time < MIXAd760xSGDef.DEFAULT_TIMEOUT):
time.sleep(MIXAd760xSGDef.DELAY_1MS)
reg_data = self.axi4_bus.read_8bit_inc(
MIXAd760xSGDef.BUSY_STAT_REG, 1)[0]
if time.time() - last_time >= MIXAd760xSGDef.DEFAULT_TIMEOUT:
raise MIXAd760xSGException('AD706X read register wait timeout')
# read channel voltage
voltages = []
volt_reg_addr = MIXAd760xSGDef.CHANNEL_VOLTAGE_BASE_REG
for i in range(self.channel_num):
rd_data = self.axi4_bus.read_8bit_inc(volt_reg_addr, 4)
volt_temp = DataOperate.list_2_int(rd_data)
if (adc_range == '10V'):
volt_temp = float(
volt_temp
) / MIXAd760xSGDef.FULL_SCALE * MIXAd760xSGDef.CONVERT_RATIO_10V
else:
volt_temp = float(
volt_temp
) / MIXAd760xSGDef.FULL_SCALE * MIXAd760xSGDef.CONVERT_RATIO_5V
volt_reg_addr += MIXAd760xSGDef.VOLTAGE_REG_OFFSET
# Convert result unit 'V' to 'mV'
volt_temp *= MIXAd760xSGDef.VOLT_2_MILLIVOLT
voltages.append(volt_temp)
return voltages
class MIXAxiLiteToStreamSG(object):
'''
MIXAxiLiteToStreamSG class provides a read/write interface for the stream bus.
ClassType = MIXAxiLiteToStreamSG
Args:
axi4_bus: instance(AXI4LiteBus)/string/None, AXI4 lite bus instance or device path;
If None, will create Emulator.
Examples:
mix_axil2s = MIXAxiLiteToStreamSG('/dev/MIX_AxiLiteToStream_0')
'''
rpc_public_api = ['write', 'read']
def __init__(self, axi4_bus=None):
if axi4_bus is None:
self.axi4_bus = AXI4LiteBusEmulator(
"mix_axilitetostream_sg_emulator", MIXAxiLiteToStreamSGDef.REGISTER_SIZE)
elif isinstance(axi4_bus, basestring):
# device path passed in; create axi4litebus here.
self.axi4_bus = AXI4LiteBus(axi4_bus, MIXAxiLiteToStreamSGDef.REGISTER_SIZE)
else:
self.axi4_bus = axi4_bus
self.__data_deal = DataOperate()
def write(self, write_data):
'''
MIXAxiLiteToStreamSG write data to stream bus
Args:
data: list, Datas to be write.
Examples:
mix_axil2s.write([0x01, 0x02, 0x03, 0x04])
'''
rd_data = self.axi4_bus.read_8bit_inc(MIXAxiLiteToStreamSGDef.WRITE_WIDTH_IPCORE_ADDR, 1)
bits_width = rd_data[0]
if(len(write_data) % 4 > 0):
raise MIXAxiLiteToStreamSGException('write data length error')
i = int(len(write_data) / bits_width)
wr_data_index = 0
if bits_width == 1:
axi4_bus_write = self.axi4_bus.write_8bit_fix
elif bits_width == 2:
axi4_bus_write = self.axi4_bus.write_16bit_fix
else:
axi4_bus_write = self.axi4_bus.write_32bit_fix
write_data_list = []
for temp in range(i):
temp_data = write_data[bits_width * temp: bits_width * (temp + 1)]
temp_data = self.__data_deal.list_2_int(temp_data)
write_data_list.append(temp_data)
while(i > 0):
rd_data = self.axi4_bus.read_8bit_inc(MIXAxiLiteToStreamSGDef.EMPTY_FIFO_NUMBER_IPCORE_ADDR, 2)
cache_deep = self.__data_deal.list_2_int(rd_data)
if(cache_deep > i):
send_cnt = i
else:
send_cnt = cache_deep - 3
axi4_bus_write(MIXAxiLiteToStreamSGDef.WRITE_FIFO_IPCORE_ADDR, write_data_list[wr_data_index:send_cnt])
wr_data_index += send_cnt
i -= send_cnt
def read(self):
'''
MIXAxiLiteToStreamSG read data from stream bus
Returns:
list, value.
Examples:
mix_axil2s.read()
'''
rd_data = self.axi4_bus.read_8bit_inc(MIXAxiLiteToStreamSGDef.READ_WIDTH_IPCORE_ADDR, 1)
bits_width = rd_data[0]
rd_data = self.axi4_bus.read_8bit_inc(MIXAxiLiteToStreamSGDef.READ_FIFO_NUMBER_IPCORE_ADDR, 2)
cache_deep = self.__data_deal.list_2_int(rd_data)
read_data = []
if bits_width == 1:
axi4_bus_read = self.axi4_bus.read_8bit_fix
elif bits_width == 2:
axi4_bus_read = self.axi4_bus.read_16bit_fix
else:
axi4_bus_read = self.axi4_bus.read_32bit_fix
if cache_deep != 0:
read_data = axi4_bus_read(MIXAxiLiteToStreamSGDef.READ_FIFO_IPCORE_ADDR, cache_deep)
return read_data
else:
return None
class MIXDMM101SGR(object):
'''
MIXDMM101SGR class provide function to enable, disable.
MIXDMM101SGR can set sampling rate, select channel and return what data received.
ClassType = MIXDMM101SGR
Args:
axi4_bus: instance(AXI4LiteBus)/string/None, AXI4 lite bus instance or device path.
Examples:
mixdmm101sgr = MIXDMM101SGR('/dev/MIX_LTC2386_SG')
mixdmm101sgr.enable()
mixdmm101sgr.set_sampling_rate(10000000)
mixdmm101sgr.channel_select('CHAB', '18bit')
volt = mixdmm101sgr.read_volt()
print(volt)
'''
rpc_public_api = [
'enable', 'disable', 'set_sampling_rate', 'channel_select',
'read_volt', 'get_continuous_sampling_voltage'
]
def __init__(self, axi4_bus):
if isinstance(axi4_bus, basestring):
# create axi4lite bus from given device path
self.axi4_bus = AXI4LiteBus(axi4_bus, MIXDMM101SGRDef.REG_SIZE)
else:
self.axi4_bus = axi4_bus
self._data_deal = DataOperate()
self.signal_meter = None
self.sample_rate = MIXDMM101SGRDef.FREQ_MAX
self.enable()
def enable(self):
'''
MIXDMM101SGR enable function
Examples:
mixdmm101sgr.enable()
'''
self.axi4_bus.write_8bit_inc(MIXDMM101SGRDef.MODULE_EN_REG, [0x00])
self.axi4_bus.write_8bit_inc(MIXDMM101SGRDef.MODULE_EN_REG, [0x01])
self.signal_meter_axi4_bus = AXI4LiteSubBus(
self.axi4_bus, MIXDMM101SGRDef.SIGNAL_METER_OFFSET_ADDR,
MIXDMM101SGRDef.SIGNAL_METER_REG_SIZE)
self.signal_meter = MIXSignalMeterSG(self.signal_meter_axi4_bus)
def disable(self):
'''
MIXDMM101SGR disable function
Examples:
mixdmm101sgr.disable()
'''
self.axi4_bus.write_8bit_inc(MIXDMM101SGRDef.MODULE_EN_REG, [0x00])
def set_sampling_rate(self, sample_rate):
'''
Set adc sample rate
Args:
sampling_rate: int, [20000~10000000], unit SPS, ADC sample rate.
Examples:
mixdmm101sgr.set_sampling_rate(10000000)
'''
assert MIXDMM101SGRDef.FREQ_MIN <= sample_rate <= MIXDMM101SGRDef.FREQ_MAX
self.sample_rate = sample_rate
freq_hz_ctrl = int(self.sample_rate * math.pow(2, 32) / 125000000)
wr_data = self._data_deal.int_2_list(freq_hz_ctrl, 4)
self.axi4_bus.write_8bit_inc(MIXDMM101SGRDef.SAMPLE_CTRL_REG, wr_data)
def channel_select(self, channel='CHA', adc_resolution='18bit'):
'''
Select adc channel
Args:
channel: string, ['CHA', 'CHAB'], default 'CHA',
'CHA' means enable adc channel A, 'CHAB' means enable adc channel A and channel B.
adc_resolution: string, ['16bit', '18bit'], default '18bit',
'16bit' means adc resolution is 16bit, '18bit' means adc resolution is 18bit.
Examples:
mixdmm101sgr.channel_select('CHAB', '18bit')
'''
channel_en = MIXDMM101SGRDef.CHANNEL_SELECT_INFO['channel_en'][channel]
adc_clk_number = MIXDMM101SGRDef.CHANNEL_SELECT_INFO['adc_clk_number'][
channel][adc_resolution]
self.axi4_bus.write_8bit_inc(MIXDMM101SGRDef.CHANNEL_SELECT_REG,
[channel_en])
self.axi4_bus.write_8bit_inc(MIXDMM101SGRDef.CLK_NUMBER_CNT_REG,
[adc_clk_number])
def read_volt(self):
'''
Get sample data
Returns:
sample_volt: float, [-1.0~1.0], the reference voltage is not multiplied,
so the return value is only a normalize volt.
Examples:
volt = mixdmm101sgr.read_volt()
print(volt)
'''
rd_data = self.axi4_bus.read_8bit_inc(MIXDMM101SGRDef.SAMPLE_DATA_REG,
4)
sample_data = self._data_deal.list_2_int(rd_data)
sample_volt = sample_data * 1.0 / math.pow(2, 31)
return sample_volt
def get_continuous_sampling_voltage(self, count):
'''
Get continuous sampling voltage
Args:
count: int, [1~2048], how many data to get.
Returns:
list, [value, ...], the unit of elements in the list is V, range is -1v~1v.
Examples:
volt_list = mixdmm101sgr.get_continuous_sampling_voltage(20)
print(volt_list)
'''
assert 1 <= count <= 2048
wait_steady_count = 10
timeout = (1.0 / self.sample_rate) * (count + wait_steady_count)
wr_data = self._data_deal.int_2_list(count, 2)
self.axi4_bus.write_8bit_inc(MIXDMM101SGRDef.CAPTURE_CNT_REG, wr_data)
self.axi4_bus.write_8bit_inc(MIXDMM101SGRDef.CAPTURE_STATE_REG, [0x00])
self.axi4_bus.write_8bit_inc(MIXDMM101SGRDef.CAPTURE_STATE_REG, [0x01])
start_time = time.time()
while True:
rd_data = self.axi4_bus.read_8bit_inc(
MIXDMM101SGRDef.CAPTURE_STATE_REG, 1)
if rd_data[0] == 0x00:
break
if time.time() - start_time >= timeout:
raise MIXDMM101SGRException('capture data time out')
break
time.sleep(0.001)
get_raw_data = []
get_voltage = []
get_raw_data = self.axi4_bus.read_32bit_fix(
MIXDMM101SGRDef.CAPTURE_DATA_REG, count * 4)
for i in range(count):
get_raw_data_temp = self._data_deal.list_2_int(
get_raw_data[i * 4:i * 4 + 4])
get_voltage.append(get_raw_data_temp * 1.0 / math.pow(2, 31))
return get_voltage
class MIXLTC2386SG(object):
'''
MIXLTC2386SG class provide function to enable, disable.
MIXLTC2386SG can set sampling rate, select channel and return what data received.
ClassType = MIXLTC2386SG
Args:
axi4_bus: instance(AXI4LiteBus)/string/None, AXI4 lite bus instance or device path.
Examples:
mixltc2386sg = MIXLTC2386SG('/dev/MIX_LTC2386_SG')
mixltc2386sg.enable()
mixltc2386sg.set_sampling_rate(10000000)
mixltc2386sg.channel_select('CHAB', '18bit')
volt = mixltc2386sg.read_volt()
print(volt)
'''
rpc_public_api = ['enable', 'disable', 'set_sampling_rate', 'channel_select', 'read_volt']
def __init__(self, axi4_bus):
if isinstance(axi4_bus, basestring):
# create axi4lite bus from given device path
self.axi4_bus = AXI4LiteBus(axi4_bus, MIXLTC2386SGDef.REG_SIZE)
else:
self.axi4_bus = axi4_bus
self._data_deal = DataOperate()
def enable(self):
'''
MIXLTC2386SG enable function
Examples:
mixltc2386sg.enable()
'''
self.axi4_bus.write_8bit_inc(MIXLTC2386SGDef.MODULE_EN_REG, [0x00])
self.axi4_bus.write_8bit_inc(MIXLTC2386SGDef.MODULE_EN_REG, [0x01])
def disable(self):
'''
MIXLTC2386SG disable function
Examples:
mixltc2386sg.disable()
'''
self.axi4_bus.write_8bit_inc(MIXLTC2386SGDef.MODULE_EN_REG, [0x00])
def set_sampling_rate(self, sample_rate):
'''
Set adc sample rate
Args:
sampling_rate: int, [20000~10000000], unit SPS, ADC sample rate.
Examples:
mixltc2386sg.set_sampling_rate(10000000)
'''
assert MIXLTC2386SGDef.FREQ_MIN <= sample_rate <= MIXLTC2386SGDef.FREQ_MAX
freq_hz_ctrl = int(sample_rate * math.pow(2, 32) / 125000000)
wr_data = self._data_deal.int_2_list(freq_hz_ctrl, 4)
self.axi4_bus.write_8bit_inc(MIXLTC2386SGDef.SAMPLE_CTRL_REG, wr_data)
def channel_select(self, channel='CHA', adc_resolution='18bit'):
'''
Select adc channel
Args:
channel: string, ['CHA', 'CHAB'], default 'CHA',
'CHA' means enable adc channel A, 'CHAB' means enable adc channel A and channel B.
adc_resolution: string, ['16bit', '18bit'], default '18bit',
'16bit' means adc resolution is 16bit, '18bit' means adc resolution is 18bit.
Examples:
mixltc2386sg.channel_select('CHAB', '18bit')
'''
channel_en = MIXLTC2386SGDef.CHANNEL_SELECT_INFO['channel_en'][channel]
adc_clk_number = MIXLTC2386SGDef.CHANNEL_SELECT_INFO['adc_clk_number'][channel][adc_resolution]
self.axi4_bus.write_8bit_inc(MIXLTC2386SGDef.CHANNEL_SELECT_REG, [channel_en])
self.axi4_bus.write_8bit_inc(MIXLTC2386SGDef.CLK_NUMBER_CNT_REG, [adc_clk_number])
def read_volt(self):
'''
Get sample data
Returns:
sample_volt: float, [-1.0~1.0], the reference voltage is not multiplied,
so the return value is only a normalize volt.
Examples:
volt = mixltc2386sg.read_volt()
print(volt)
'''
rd_data = self.axi4_bus.read_8bit_inc(MIXLTC2386SGDef.SAMPLE_DATA_REG, 4)
sample_data = self._data_deal.list_2_int(rd_data)
sample_volt = sample_data * 1.0 / math.pow(2, 31)
return sample_volt
class PLSPIDAC(object):
'''
Axi4 spi dac function class to control the spi dac
ClassType = PLSPIDAC
Args:
axi4_bus: instance(AXI4LiteBus)/None, Class instance of AXI4 bus,
If not using this parameter,
will create Emulator
Examples:
spi_dac = PLSPIDAC('/dev/MIX_SPI_DAC')
'''
rpc_public_api = ['open', 'close', 'dac_mode_set', 'spi_sclk_frequency_set',
'sample_data_set', 'test_register', 'set_axi4_clk_frequency']
def __init__(self, axi4_bus=None):
if axi4_bus is None:
self.axi4_bus = AXI4LiteBusEmulator(
"pl_spi_dac_emulator", PLSPIDACDef.REG_SIZE)
elif isinstance(axi4_bus, basestring):
# device path passed in; create axi4litebus here.
self.axi4_bus = AXI4LiteBus(axi4_bus, PLSPIDACDef.REG_SIZE)
else:
self.axi4_bus = axi4_bus
self.dev_name = self.axi4_bus._dev_name
self.reg_num = 256
self.axi4_clk_frequency = 125000000
self.data_deal = DataOperate()
self.sclk_frequency = 10000000
self.open()
def __del__(self):
self.close()
def open(self):
'''
Axi4 spi dac open
Examples:
spi_dac.open()
'''
self.axi4_bus.write_8bit_inc(PLSPIDACDef.CONFIG_REGISTER, [0x00])
self.axi4_bus.write_8bit_inc(PLSPIDACDef.CONFIG_REGISTER, [0x01])
def close(self):
'''
Axi4 spi dac close
Examples:
spi_dac.close()
'''
self.axi4_bus.write_8bit_inc(PLSPIDACDef.CONFIG_REGISTER, [0x00])
def dac_mode_set(self, dac_mode):
'''
Axi4 spi dac mode set
Args:
dac_mode: int, set dac mode.
Examples:
spi_dac.dac_mode_set(0x12)
'''
wr_data = [dac_mode]
self.axi4_bus.write_8bit_inc(
PLSPIDACDef.DAC_MODE_SET_REGISTER, wr_data)
def spi_sclk_frequency_set(self, sclk_freq_hz):
'''
Axi4 spi dac set sclk frequency
Args:
sclk_freq_hz: int, unit Hz, set sclk frequency.
Examples:
spi_dac.spi_sclk_frequency_set(3000)
'''
self.sclk_frequency = sclk_freq_hz
freq_hz_ctrl = int(sclk_freq_hz * pow(2, 32) /
self.axi4_clk_frequency)
wr_data = self.data_deal.int_2_list(freq_hz_ctrl, 4)
self.axi4_bus.write_8bit_inc(
PLSPIDACDef.FREQUENCY_SET_REGISTER, wr_data)
def sample_data_set(self, sample_rate):
'''
Axi4 spi dac set sample data
Args:
sample_rate: int, unit Hz, set sample data.
Examples:
spi_dac.sample_data_set(3000)
'''
freq_hz_ctrl = int(sample_rate * pow(2, 32) / self.sclk_frequency)
wr_data = self.data_deal.int_2_list(freq_hz_ctrl, 4)
self.axi4_bus.write_8bit_inc(
PLSPIDACDef.SAMPLE_DATA_SET_REGISTER, wr_data)
def test_register(self, test_data):
'''
Axi4 spi dac test register
Args:
test_data: int, test data.
Examples:
self.test_register(30)
'''
wr_data = self.data_deal.int_2_list(test_data, 4)
self.axi4_bus.write_8bit_inc(PLSPIDACDef.CONFIG_REGISTER, wr_data)
rd_data = self.axi4_bus.read_8bit_inc(
PLSPIDACDef.CONFIG_REGISTER, len(wr_data))
test_out = self.data_deal.list_2_int(rd_data)
if(test_out != test_data):
raise PLSPIDACException(
self.dev_name, 'Test Register read data error. ')
return False
def set_axi4_clk_frequency(self, clk_frequency):
'''
Axi4 spi dac set axi4 clock frequency
Args:
clk_frequency: int, clock frequency.
Examples:
spi_dac.set_axi4_clk_frequency(50000)
'''
self.axi4_clk_frequency = clk_frequency