def m_fifo_ramp( # --[ports]-- # @todo: use glbl for clock and reset clock, reset, regbus, fifobus, # --[parameters]-- base_address=0x00): """ FIFO Ramp module This module provides a simple 8-bit counter that will generate a ramp. This ramp is fed to the USB fifo. This can be used to validate the usb connection and the device to host (IN) data rates. """ glbl = Global(clock=clock, reset=reset) g_regbus = regbus.add(glbl, regfile, 'fifo_ramp', base_address) enable = Signal(False) ramp = Signal(intbv(0)[fifobus.width:]) wcnt = Signal(intbv(0x3FF)[32:]) div = Signal(intbv(0)[32:]) rcnt = Signal(intbv(0)[32:]) # ?? not sure if this makes sense ?? ramp_mod = int(2**fifobus.width) @always_comb def rtl_assign(): regfile.cnt3.next = (rcnt >> 24) & 0xFF regfile.cnt2.next = (rcnt >> 16) & 0xFF regfile.cnt1.next = (rcnt >> 8) & 0xFF regfile.cnt0.next = (rcnt >> 0) & 0xFF @always_seq(clock.posedge, reset=reset) def rtl_reg(): enable.next = regfile.enable div.next = ((regfile.div3 << 24) | (regfile.div2 << 16) | (regfile.div1 << 8) | (regfile.div0)) @always_seq(clock.posedge, reset=reset) def rtl_ramp(): if regfile.enable and not fifobus.full: if wcnt == 0: fifobus.wr.next = True fifobus.wdata.next = ramp if ramp + 1 == ramp_mod: rcnt.next = rcnt + 1 ramp.next = (ramp + 1) % ramp_mod wcnt.next = div else: fifobus.wr.next = False wcnt.next = wcnt - 1 else: fifobus.wr.next = False fifobus.wdata.next = 0 wcnt.next = div return instances()
def m_btn_led_mm(clock, reset, leds, btns, bus_type='W'): """ A toy example to demostrate bus agnosticism This example instantiates a memory-map controller and a memory-map peripheral. This example shows how the controllers and peripherals can be passed the memmap interface. The passing of the interface allows the modules (components) to be bus agnostic. This example solves a simple task in a complicated manner to show the point. When a button press is detected a bus cycle is generated to write the "flash" pattern to the LED peripheral. Note: for easy FPGA bit-stream generation the port names match the board names defined in the *gizflo* board definitions. """ glbl = Global(clock=clock, reset=reset) if bus_type == 'B': regbus = Barebone(glbl, data_width=8, address_width=16) elif bus_type == 'W': regbus = Wishbone(glbl, data_width=8, address_width=16) elif bus_type == 'A': regbus = AvalonMM(glbl, data_width=8, address_width=16) #elif bus_type == 'X': # regbus = AXI4(glbl, data_wdith=8, address_width=16) gbtn = m_btn_mm_ctl(glbl, regbus, btns) # memmap controller gled = m_led_mm_per(glbl, regbus, leds) # memmap peripheral gmap = regbus.m_per_outputs() # bus combiner print(vars(regbus.regfiles['LED_000'])) return gbtn, gled, gmap
def convert(args): glbl = Global(frequency=50e6) vmem = VideoMemory() toVerilog(m_color_bars, glbl, vmem, resolution=args.res, width=args.width) toVHDL(m_color_bars, glbl, vmem, resolution=args.res, width=args.width)
def mm_vgasys( # ~~~[PORTS]~~~ clock, reset, vselect, hsync, vsync, red, green, blue, pxlen, active, # ~~~~[PARAMETERS]~~~~ resolution=( 640, 480, ), color_depth=( 10, 10, 10, ), refresh_rate=60, line_rate=31250): # create the system-level signals, overwrite clock, reset glbl = Global(clock=clock, reset=reset) # VGA inteface vga = VGA(hsync=hsync, vsync=vsync, red=red, green=green, blue=blue, pxlen=pxlen, active=active) # video memory interface vmem = VideoMemory() # instances of modules gbar = m_color_bars(glbl, vmem, resolution=resolution) gvga = m_vga_sync(glbl, vga, vmem, resolution=resolution, refresh_rate=refresh_rate, line_rate=line_rate) return gvga, gbar
def test_register_file(): global regfile # top-level signals and interfaces clock = Clock(0, frequency=50e6) reset = Reset(0, active=1, async=False) glbl = Global(clock, reset) regbus = Wishbone(glbl) def _test_rf(): tb_dut = m_per(glbl, regbus, 0xAA) tb_or = regbus.m_per_outputs() tb_mclk = clock.gen() tb_rclk = regbus.clk_i.gen() asserr = Signal(bool(0)) @instance def tb_stim(): try: yield delay(100) yield reset.pulse(111) for k,reg in regdef.iteritems(): if reg.access == 'ro': yield regbus.read(reg.addr) rval = regbus.readval assert rval == reg.default, "ro: %02x != %02x"%(rwd.rval,reg.default) else: wval = randint(0,(2**reg.width)-1) yield regbus.write(reg.addr, wval) for _ in xrange(4): yield clock.posedge yield regbus.read(reg.addr) rval = regbus.readval assert rval == wval, "rw: %02x != %02x"%(rwd.rval,rwd.wval) yield delay(100) except AssertionError,err: print("@E: %s" % (err,)) traceback.print_exc() asserr.next = True for _ in xrange(10): yield clock.posedge raise err raise StopSimulation return tb_mclk, tb_stim, tb_dut, tb_or, tb_rclk
def _test(): # top-level VGA system tbdut = mm_vgasys(clock, reset, vselect, vga.hsync, vga.vsync, vga.red, vga.green, vga.blue, vga.pxlen, vga.active, resolution=res, refresh_rate=refresh_rate, line_rate=line_rate) # group global signals glbl = Global(clock=clock, reset=reset) # a display for each dut mvd = VideoDisplay(frequency=clock.frequency, resolution=res, refresh_rate=refresh_rate, line_rate=line_rate) # connect VideoDisplay model to the VGA signals tbvd = mvd.process(glbl, vga) # clock generator tbclk = clock.gen() @instance def tbstim(): reset.next = reset.active yield delay(18) reset.next = not reset.active # Wait till a full screen has been updated while mvd.update_cnt < 1: yield delay(1000) # @todo: verify video system memory is correct! # (self checking!) raise StopSimulation return tbclk, tbvd, tbstim, tbdut
def _test(): ibus = Wishbone() extmem = SDRAM(clock) print(vars(extmem)) tbdut = m_sdram(clock, reset, ibus, extmem) glbl = Global(clock=clock, reset=reset) tbclk = clock.gen() @instance def tbstim(): reset.next = reset.active yield delay(18) reset.next = not reset.active for ii in range(100): yield delay(1000) raise StopSimulation return tbclk, tbdut, tbstim
def test_register_file_bits(): global regfile # top-level signals and interfaces clock = Clock(0, frequency=50e6) reset = Reset(0, active=1, async=False) glbl = Global(clock, reset) regbus = Wishbone(glbl) def _test(): tb_dut = m_per_bits(glbl, regbus, 0xAA) tb_or = regbus.m_per_outputs() tb_mclk = clock.gen() tb_rclk = regbus.clk_i.gen() asserr = Signal(bool(0)) @instance def tb_stim(): regfile.ok.next = True try: yield reset.pulse(111) yield clock.posedge yield clock.posedge truefalse = True yield regbus.write(regfile.control.addr, 0x01) for _ in xrange(100): assert (regfile.enable, regfile.loop) == (truefalse, not truefalse) yield regbus.read(regfile.control.addr) yield regbus.write(regfile.control.addr, ~regbus.readval) truefalse = not truefalse yield clock.posedge except AssertionError, err: asserr.next = True for _ in xrange(20): yield clock.posedge raise err raise StopSimulation return tb_mclk, tb_stim, tb_dut, tb_or, tb_rclk
def test_fifo_ramp(): clock = Clock(0, frequency=50e6) reset = Reset(0, active=1, async=False) glbl = Global(clock, reset) regbus = Wishbone(glbl) fifobus = FIFOBus() def _test_fifo_ramp(): tb_dut = m_fifo_ramp(clock, reset, regbus, fifobus, base_address=0x0000) tb_rbor = regbus.m_per_outputs() tb_clk = clock.gen() asserr = Signal(bool(0)) @instance def tb_stim(): try: yield delay(100) yield reset.pulse(111) # simply enable, enable the module and then # verify an incrementing pattern over the # fifobus yield regbus.write(0x00, 1) yield regbus.read(0x00) assert 1 == regbus.readval, "cfg reg write failed" # monitor the bus until ?? ramps Nramps, rr = 128, 0 while rr < Nramps: cnt = 0 for ii, sh in enumerate(( 24, 16, 8, 0, )): yield regbus.read(0x08 + ii) cnt = cnt | (regbus.readval << sh) rr = cnt except AssertionError, err: asserr.next = True for _ in xrange(10): yield clock.posedge raise err raise StopSimulation # monitor the values from the fifo bus, it should # be a simple "ramp" increasing values _mask = 0xFF _cval = Signal(modbv(0, min=0, max=256)) @always(clock.posedge) def tb_mon(): if fifobus.wr: assert _cval == fifobus.wdata _cval.next = _cval + 1 return tb_clk, tb_dut, tb_stim, tb_mon, tb_rbor
def m_per_top(clock, reset, mon): glbl = Global(clock, reset) wb = Wishbone(glbl) #gpm = wb.m_controller(wb) gp1 = m_per(glbl, wb, mon) return gp1
def test_spi(): base_address = ba = 0x400 clock = Clock(0, frequency=50e6) reset = Reset(0, active=1, async=False) glbl = Global(clock, reset) regbus = Wishbone(glbl) fiforx,fifotx = FIFOBus(size=16), FIFOBus(size=16) spiee = SPIEEPROM() spibus = SPIBus() asserr = Signal(bool(0)) def _test_spi(): tbdut = m_spi(glbl, regbus, fiforx, fifotx, spibus, base_address=base_address) tbeep = spiee.gen(clock, reset, spibus) tbclk = clock.gen(hticks=5) # grab all the register file outputs tbmap = regbus.m_per_outputs() # get a reference to the SPI register file rf = regbus.regfiles['SPI_000'] # dumpy the registers for the SPI peripheral for name,reg in rf.registers.iteritems(): print("{0} {1:04X} {2:04X}".format(name, reg.addr, int(reg))) @instance def tbstim(): yield reset.pulse(33) try: #~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ # loop through the registers and check the default # values, these are the offset values. for addr,sig in rf.roregs: yield regbus.read(addr+ba) assert regbus.readval == int(sig) for addr,sig in rf.rwregs: # need to skip the FIFO read / write if addr in (0x68, 0x6C,): pass else: yield regbus.read(addr+ba) assert regbus.readval == int(sig) #~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ # enable the system print(" enable the SPI core") yield regbus.write(rf.spst.addr, 0x02) # register data drives fifo yield regbus.write(rf.spcr.addr, 0x9A) # default plus enable (98 + 02) print(" write to the transmit register") yield regbus.write(rf.sptx.addr, 0x02) yield regbus.write(rf.sptx.addr, 0x00) yield regbus.write(rf.sptx.addr, 0x00) yield regbus.write(rf.sptx.addr, 0x00) yield regbus.write(rf.sptx.addr, 0x55) yield regbus.read(rf.sptc.addr) print(regbus.readval) yield regbus.read(rf.sprc.addr) print(regbus.readval) yield delay(1000) for ii in range(1000): yield regbus.read(rf.sprc.addr) if regbus.readval == 5: break yield delay(1000) for ii in range(5): yield regbus.read(rf.sprx.addr) print("spi readback {0}".format(regbus.readval)) except Exception, err: print("@W: exception {0}".format(err)) yield delay(100) raise err yield delay(100) raise StopSimulation return tbstim, tbdut, tbeep, tbclk, tbmap