def WriteWithDelay(self): if (GlobalOptions.dryrun): return logger.info("Writing Qstate @0x%x Type: %s size: %d with delay" % (self.addr, self.queue_type, self.size)) model_wrap.write_mem_pcie(self.addr, bytes(self.data), len(self.data)) # On RTL, write is asyncronous and taking long time to complete # Wait until the write succeed otherwise tests may fail in RTL (timing) # Read(synchrouns) in loop and wait until the read data is same as what was inteded to write # Be aware this logic would break if there is continous change to QStata data in hardware # like spruious schdule count in qstate, etc. wdata = self.data[0:64] if GlobalOptions.rtl: count = 1 while True: self.data = qt_params[self.queue_type]['state']( model_wrap.read_mem(self.addr, self.size)) rdata = self.data[0:64] if rdata == wdata: break # Read data is not same as we wrote, so sleep for 1 sec and try again time.sleep(1) count = count + 1 logger.info( "Qstate Write @0x%x Type: %s size: %d completed after %d secs" % (self.addr, self.queue_type, self.size, count))
def Write(self, lgh=logger): if GlobalOptions.skipverify: return lgh.info("Writing %s @0x%x size: %d" % (self.__data_class__.__name__, self.addr, self.size)) model_wrap.write_mem_pcie(self.addr, bytes(self.data), len(self.data)) self.Read(lgh)
def WriteAtomicResData(self): if (GlobalOptions.dryrun): return logger.info("Writing Atomic resource address @0x%x size: %d" % (self.rdma_atomic_res_addr, 64)) model_wrap.write_mem_pcie(self.rdma_atomic_res_addr, bytes(self.atomic_res_data), 64) self.ReadAtomicResData() return
def WriteRomeSenderCb(self): if (GlobalOptions.dryrun): return # rome_sender_cb is located after header_template. header_template is 66 bytes len and 1 byte ah_size. logger.info("Writing ROME_SENDER Qstate @0x%x size: %d" % (self.header_temp_addr + AH_ENTRY_T_SIZE_BYTES, ROME_CB_T_SIZE_BYTES)) model_wrap.write_mem_pcie( self.header_temp_addr + AH_ENTRY_T_SIZE_BYTES, bytes(self.rome_sender_data), ROME_CB_T_SIZE_BYTES) self.ReadRomeSenderCb() return
def WriteDcqcnCb(self): if (GlobalOptions.dryrun): return # dcqcn_cb is located after header_template. header_template is 66 bytes len and 1 byte ah_size. logger.info("Writing DCQCN Qstate @0x%x size: %d" % (self.header_temp_addr + AH_ENTRY_T_SIZE_BYTES, DCQCN_CB_T_SIZE_BYTES)) model_wrap.write_mem_pcie( self.header_temp_addr + AH_ENTRY_T_SIZE_BYTES, bytes(self.dcqcn_data), DCQCN_CB_T_SIZE_BYTES) self.ReadDcqcnCb() return
def WriteRomeReceiverCb(self): if (GlobalOptions.dryrun): return # rome_receiver_cb is located after ah table and dcqcn table. header_template is 66 bytes len and 1 byte ah_size. logger.info("Writing ROME_RECEIVER Qstate @0x%x size: %d" % (self.header_temp_addr + AH_ENTRY_T_SIZE_BYTES + DCQCN_CB_T_SIZE_BYTES, ROME_CB_T_SIZE_BYTES)) model_wrap.write_mem_pcie( self.header_temp_addr + AH_ENTRY_T_SIZE_BYTES + DCQCN_CB_T_SIZE_BYTES, bytes(self.rome_receiver_data), ROME_CB_T_SIZE_BYTES) self.ReadRomeReceiverCb() return
def Write(self, lgh=logger): if GlobalOptions.skipverify: return # post devcmd data = self.data[self.__data_class__] # set cmd done data.done = 0 # set doorbell data.doorbell = 1 lgh.info("Writing %s @0x%x size: %d" % (self.__data_class__.__name__, self.addr, self.size)) self.Show() model_wrap.write_mem_pcie(self.addr, bytes(self.data), len(self.data)) # wait for nicmgr to process this devcmd utils.Sleep(NICMGR_DEV_CMD_TIMEOUT)
def Write(self): """ Creates a Descriptor at "self.address" :return: """ desc = NvmeTcprqDescriptor() self.desc = desc logger.ShowScapyObject(desc) logger.info("desc_size = %d" % (len(desc))) if self.mem_handle: resmgr.HostMemoryAllocator.write(self.mem_handle, bytes(desc)) else: model_wrap.write_mem_pcie(self.address, bytes(desc), len(desc)) #TBD: Do we need it ? self.Read()
def WriteWithDelay(self): if (GlobalOptions.dryrun): return logger.info("Writing RdmaDcqcnProfile @0x%x size: %d with delay" % (self.addr, self.size)) model_wrap.write_mem_pcie(self.addr, bytes(self.data), len(self.data)) # On RTL, write is asyncronous and taking long time to complete # Wait until the write succeed otherwise tests may fail in RTL (timing) # Read(synchrouns) in loop and wait until the read data is same as what was inteded to write wdata = self.data[0:len(self.data)] if GlobalOptions.rtl: count = 1 while True: self.Read() rdata = self.data[0:len(self.data)] if rdata == wdata: break # Read data is not same as we wrote, so sleep for 1 sec and try again time.sleep(1) count = count + 1 logger.info("RdmaDcqcnProfile Write @0x%x size: %d completed after %d secs" % (self.addr, self.size, count)) else: self.Read()
def Write(self, debug = True): if (GlobalOptions.dryrun): return if debug is True: logger.info("Writing Qstate @0x%x Type: %s size: %d" % (self.addr, self.queue_type, self.size)) model_wrap.write_mem_pcie(self.addr, bytes(self.data), len(self.data))
def Write(self): if (GlobalOptions.dryrun): return logger.info("Writing RdmaDcqcnProfile @0x%x size: %d" % (self.addr, self.size)) model_wrap.write_mem_pcie(self.addr, bytes(self.data), len(self.data)) self.Read()