def gen_model(real_type):
# create mixed-signal model
model = MixedSignalModel('model', build_dir=BUILD_DIR, real_type=real_type)
model.add_digital_input('in_', width=N_BITS)
model.add_analog_output('out')
model.add_digital_input('clk')
model.add_digital_input('rst')
# create function
domain = [map_f(0), map_f((1 << N_BITS) - 1)]
real_func = model.make_function(
lambda x: inv_cdf(unmap_f(x) / (1 << (N_BITS + 1))),
domain=domain,
order=1,
numel=512)
# apply function
mapped = compress_uint(model.in_)
model.set_from_sync_func(model.out,
real_func,
mapped,
clk=model.clk,
rst=model.rst)
# write the model
return model.compile_to_file(VerilogGenerator())
def gen_model(myfunc,
order=0,
numel=512,
real_type=RealType.FixedPoint,
func_mode='sync'):
# create mixed-signal model
model = MixedSignalModel('model', build_dir=BUILD_DIR, real_type=real_type)
model.add_analog_input('in_')
model.add_analog_output('out')
model.add_digital_input('clk')
model.add_digital_input('rst')
# create function
write_tables = (func_mode in {'sync'})
real_func = model.make_function(myfunc,
domain=[-DOMAIN, +DOMAIN],
order=order,
numel=numel,
write_tables=write_tables)
# apply function
model.set_from_func(model.out,
real_func,
model.in_,
clk=model.clk,
rst=model.rst,
func_mode=func_mode)
# write the model
return model.compile_to_file(VerilogGenerator())
def gen_model(mean=0.0,
std=1.0,
num_sigma=6.0,
order=1,
numel=512,
real_type=RealType.FixedPoint):
# create mixed-signal model
model = MixedSignalModel('model', build_dir=BUILD_DIR, real_type=real_type)
model.add_digital_input('clk')
model.add_digital_input('rst')
model.add_analog_output('real_out')
# compute the inverse CDF of the distribution (truncated to 0, 1 domain)
inv_cdf = lambda x: truncnorm.ppf(
x, -num_sigma, +num_sigma, loc=mean, scale=std)
# create the function object
inv_cdf_func = model.make_function(inv_cdf,
domain=[0.0, 1.0],
order=order,
numel=numel)
model.set_this_cycle(
model.real_out,
model.arbitrary_noise(inv_cdf_func, clk=model.clk, rst=model.rst))
# write the model
return model.compile_to_file(VerilogGenerator())
def gen_model(order, numel, build_dir):
# settings:
# order=0, numel=512 => rms_error <= 0.0105
# order=1, numel=128 => rms_error <= 0.000318
# order=2, numel= 32 => rms_error <= 0.000232
# create mixed-signal model
m = MixedSignalModel('model', build_dir=build_dir)
m.add_analog_input('in_')
m.add_analog_output('out')
# create function
real_func = m.make_function(myfunc,
domain=[-np.pi, +np.pi],
order=order,
numel=numel)
# apply function
m.set_from_sync_func(m.out, real_func, m.in_)
# write the model
return m.compile_to_file(VerilogGenerator())
