Ejemplo n.º 1
0
 def runTests(self, test):
     """Helper method to run the actual tests."""
     clk = Signal(bool(0))
     dut = ClkDriver(clk)
     check = test(clk)
     sim = Simulation(dut, check)
     dut.config_sim(trace=True)
     sim.run(100, quiet=1)
     sim.quit()
Ejemplo n.º 2
0
def issue_104_multiple_instance():
    sim1 = Simulation(test())
    sim1.run(1000)
    # sim1 is "puased"

    # try and create a second, third, forth simulation instance
    for ii in range(4):
        with raises_kind(SimulationError, _error.MultipleSim):
              another_sim = Simulation(test())
    # generating more sims should have failed
    sim1.run(1000)
    sim1.quit()
Ejemplo n.º 3
0
def issue_104_multiple_instance():
    sim1 = Simulation(test())
    sim1.run(1000)
    # sim1 is "puased"

    # try and create a second, third, forth simulation instance
    for ii in range(4):
        with raises_kind(SimulationError, _error.MultipleSim):
              another_sim = Simulation(test())
    # generating more sims should have failed
    sim1.run(1000)
    sim1.quit()
Ejemplo n.º 4
0
 def runTests(self, test):
     """Helper method to run the actual tests."""
     clk = Signal(bool(0))
     set = Signal(bool(1))
     rst = Signal(bool(1))
     d = Signal(bool(0))
     q = Signal(bool(0))
     clock_gen = ClkDriver(clk)
     dut = DFlipFlop(clk, set, rst, d, q)
     check = test(clk, set, rst, d, q)
     sim = Simulation(clock_gen, dut, check)
     #sim = Simulation(dut, check)
     dut.config_sim(trace=True)
     sim.run(100, quiet=1)
     sim.quit()
Ejemplo n.º 5
0
 def testBackupOutputFile(self, vcd_dir):
     p = "%s.vcd" % fun.__name__
     dut = traceSignals(fun)
     sim = Simulation(dut)
     sim.run(1000, quiet=QUIET)
     sim.quit()
     _simulator._tf.close()
     _simulator._tracing = 0
     size = path.getsize(p)
     pbak = p + '.' + str(path.getmtime(p))
     assert not path.exists(pbak)
     dut = traceSignals(fun)
     _simulator._tf.close()
     _simulator._tracing = 0
     assert path.exists(p)
     assert path.exists(pbak)
     assert path.getsize(pbak) == size
     assert path.getsize(p) < size
Ejemplo n.º 6
0
    def testBackupOutputFile(self, vcd_dir):
        p = "%s.vcd" % fun.__name__

        dut = traceSignals(fun())
        sim = Simulation(dut)
        sim.run(1000, quiet=QUIET)
        sim.quit()

        _simulator._tf.close()
        _simulator._tracing = 0
        size = path.getsize(p)
        pbak = p[:-4] + '.' + str(path.getmtime(p)) + '.vcd'
        assert not path.exists(pbak)
        dut = traceSignals(fun())
        _simulator._tf.close()
        _simulator._tracing = 0
        assert path.exists(p)
        assert path.exists(pbak)
        assert path.getsize(pbak) == size
        assert path.getsize(p) < size
Ejemplo n.º 7
0
    def run(self):
        """ Start the MyHDL Simulation.
        This function will start the myhdl simulator.  The myhdl simulator
        will run in a separate thread (this object).  The outside world will
        interact with the HDL simulator enviroment through the Read/Write
        functions.  These functions will send buffers (lists) to be read or
        written to the simulation enviornment.
        """
        gens = []
        # use the module/function wrapper for tracing
        tb_intf = slave_fifo(self, self.fx2_bus)

        @always(self._stop.posedge)
        def tb_mon():
            raise StopSimulation

        tb_intf.config_sim(trace=self.trace)
        gens = [tb_intf, tb_mon, self.g]
        sim = Simulation(gens)
        sim.run()
        sim.quit()
Ejemplo n.º 8
0
    def run(self):
        """ Start the MyHDL Simulation.
        This function will start the myhdl simulator.  The myhdl simulator
        will run in a separate thread (this object).  The outside world will
        interact with the HDL simulator enviroment through the Read/Write
        functions.  These functions will send buffers (lists) to be read or
        written to the simulation enviornment.
        """
        gens = []
        # use the module/function wrapper for tracing
        tb_intf = slave_fifo(self, self.fx2_bus)

        @always(self._stop.posedge)
        def tb_mon():
            raise StopSimulation

        tb_intf.config_sim(trace=self.trace)
        gens = [tb_intf, tb_mon, self.g]
        sim = Simulation(gens)
        sim.run()
        sim.quit()
Ejemplo n.º 9
0
 def testTristateTrace(self, vcd_dir):
     sim = Simulation(topTristate())
     sim.run(100, quiet=QUIET)
     sim.quit()
    pixel = [1, 0, 0]

    clock = Signal(bool(0))
    clock_drive = clock_driver(clock)

    video_interface = VideoInterface(clock, res)

    @instance
    def test():

        video_interface.reset_cursor()
        video_interface.enable_video()

        # iterating over the frame
        for _ in range(res[0]*res[1]):
            # Sending a pixel
            yield video_interface.write_pixel(pixel), \
                video_interface.read_pixel()
            assert video_interface.get_pixel() == pixel

        video_interface.disable_video()

    return clock_drive, test

test_inst = test_video_interface()

sim = Simulation(test_inst)
sim.run(10000)
sim.quit()

Ejemplo n.º 11
0
def issue_104_quit_method():
    sim = Simulation(test())
    sim.run(1000)
    sim.run(500)
    sim.quit()
    return sim._finished
Ejemplo n.º 12
0
 def testTristateTrace(self, vcd_dir):
     sim = Simulation(topTristate())
     sim.run(100, quiet=QUIET)
     sim.quit()
    clock = Signal(0)
    clock_drive = clock_driver(clock)
    aux_interface = AuxInterface(clock, aux_depth)
    aux_data = (0, 0, 0)

    @instance
    def test():

        aux_interface.enable_aux()

        # I have no idea as to what to pass as auxiliary data
        yield aux_interface.write_aux(*aux_data), \
              aux_interface.read_aux()
        assert aux_interface.get_aux_data() == aux_data

        # AUX data can be updated here
        yield aux_interface.write_aux(*aux_data), \
              aux_interface.read_aux()
        assert aux_interface.get_aux_data() == aux_data

        aux_interface.disable_aux()

    return clock_drive, test

test_instance = test_aux_interface()

sim = Simulation(test_instance)
sim.run(8)
sim.quit()
Ejemplo n.º 14
0
def issue_104_quit_method():
    sim = Simulation(test())
    sim.run(1000)
    sim.run(500)
    sim.quit()
    return sim._finished