def test_wavelet_2d(self):
image = imageio.imread(join(dirname(__file__), "che_128.png"))
h, w = image.shape
platform = SimPlatform()
m = Module()
input = ImageStream(8)
transformer = m.submodules.transformer = Wavelet2D(input, w, h)
def write_process():
yield from write_frame_to_stream(input, image, pause=False)
yield Passive()
while True:
yield from write_to_stream(input, line_last=0, frame_last=0, payload=0)
platform.add_process(write_process, "sync")
def read_process():
image = (yield from read_frame_from_stream(transformer.output, timeout=1000, pause=False))
target_image = np.copy(image)
for y, row in enumerate(image):
for x, px in enumerate(row):
target_image[y // 2 + ((y % 2) * len(image) // 2)][x // 2 + ((x % 2) * len(row) // 2)] = px
imageio.imsave(platform.output_filename_base + ".png", target_image)
platform.add_process(read_process, "sync")
platform.add_sim_clock("sync", 1000e6)
platform.sim(m)
def test_stream_splitter(self):
image = imageio.imread(join(dirname(__file__), "che_128.png"))
h, w = image.shape
platform = SimPlatform()
m = Module()
input = ImageStream(8)
transformer = m.submodules.transformer = Wavelet2D(input, w, h)
splitter = m.submodules.splitter = ImageSplitter(transformer.output, w, h)
def write_process():
yield from write_frame_to_stream(input, image, pause=False)
yield Passive()
yield from write_frame_to_stream(input, image, pause=False)
while True:
yield from write_to_stream(input, line_last=0, frame_last=0, payload=0)
platform.add_process(write_process, "sync")
for i, stream in enumerate(splitter.outputs):
def gen_read_process():
i_captured = i
stream_captured = stream
def read_process():
image = (yield from read_frame_from_stream(stream_captured, timeout=1000, pause=False))
imageio.imsave(platform.output_filename_base + "_output_{}.png".format(i_captured), image)
return read_process
platform.add_process(gen_read_process(), "sync")
platform.add_sim_clock("sync", 100e6)
platform.sim(m)
def test_gearbox_12_to_48_to_64(self):
m = Module()
platform = SimPlatform()
input = BasicStream(12)
tee = m.submodules.tee = StreamTee(input)
gear_12_to_48 = m.submodules.gear_12_to_48 = StreamGearbox(tee.get_output(), 48)
gear_48_to_64 = m.submodules.gear_48_to_64 = StreamGearbox(gear_12_to_48.output, 64)
gear_12_to_64 = m.submodules.gear_12_to_64 = StreamGearbox(tee.get_output(), 64)
def writer():
yield Passive()
random.seed(0)
while True:
yield from write_to_stream(input, payload=random.randrange(0, 2**12))
platform.add_process(writer, "sync")
def reader():
for _ in range(100):
a = yield from read_from_stream(gear_12_to_64.output)
b = yield from read_from_stream(gear_48_to_64.output)
print(f"{a:064b}")
self.assertEqual(a, b)
platform.add_process(reader, "sync")
platform.add_sim_clock("sync", 100e6)
platform.sim(m)
def test_hello_world(self):
platform = SimPlatform()
m = Module()
address_stream = PacketizedStream(8)
mem = Memory(width=32, depth=128, init=[i + 2 for i in range(128)])
reader = m.submodules.reader = StreamMemoryReader(address_stream, mem)
def write_process():
for i in range(128):
yield from write_to_stream(address_stream,
payload=i,
last=(i % 8) == 0)
yield Passive()
def read_process():
for i in range(128):
data, last = (yield from
read_from_stream(reader.output,
extract=("payload", "last")))
assert data == i + 2
assert last == ((i % 8) == 0)
yield Passive()
platform.add_sim_clock("sync", 100e6)
platform.add_process(write_process, "sync")
platform.sim(m, read_process)
def test_basic(self):
platform = SimPlatform()
m = Module()
input = PacketizedStream(8)
input_data = [1, 0, 1, *([0] * 14), 1]
run_length_options = [3, 10, 27, 80, 160]
rle = m.submodules.rle = ZeroRleEncoder(
input,
RleEncodingSpace(range(0, 255), run_length_options, zero_value=0))
def write_process():
for x in input_data:
yield from write_to_stream(input, payload=x)
def read_process():
received = []
while True:
try:
received.append((yield from read_from_stream(rle.output)))
except TimeoutError:
break
decoded = []
for x in received:
if x < 256:
decoded.append(x)
else:
decoded += ([0] * run_length_options[x - 256])
self.assertEqual(input_data, decoded)
platform.add_sim_clock("sync", 100e6)
platform.add_process(write_process, "sync")
platform.sim(m, read_process)
def test_simple_gearbox_384_to_64_last(self):
input = PacketizedStream(32 * 12)
dut = SimpleStreamGearbox(input, 64)
payload_a = int("".join(reversed([f"{i:03x}" for i in range(32)])), 16)
payload_b = int("".join(reversed([f"{i:03x}" for i in range(57, 57 + 32)])), 16)
print(hex(payload_a))
print(hex(payload_b))
def writer():
yield from write_to_stream(input, payload=payload_a, last=1)
yield from write_to_stream(input, payload=payload_b, last=0)
def reader():
payload_aa = payload_a
for i in range(32 * 12 // 64):
self.assertEqual((yield from read_from_stream(dut.output, extract=("payload", "last"))), (payload_aa & 0xffff_ffff_ffff_ffff, 0 if i < 5 else 1))
payload_aa = payload_aa >> 64
payload_bb = payload_b
for i in range(32 * 12 // 64):
print(i)
self.assertEqual((yield from read_from_stream(dut.output, extract=("payload", "last"))), (payload_bb & 0xffff_ffff_ffff_ffff, 0))
payload_bb = payload_bb >> 64
platform = SimPlatform()
platform.add_sim_clock("sync", 100e6)
platform.add_process(writer, "sync")
platform.add_process(reader, "sync")
platform.sim(dut)
def test_simple_gearbox_dont_loose_last_16_to_4(self):
input = PacketizedStream(16)
dut = SimpleStreamGearbox(input, 4)
def writer():
last_count_gold = 0
for i in range(50):
last = (i % 5 == 0)
last_count_gold += last
yield from write_to_stream(input, payload=0, last=(i % 5 == 0))
if i % 3 == 0:
yield from do_nothing()
self.assertEqual(last_count_gold, 10)
def reader():
last_count = 0
for i in range(200):
last_count += (yield from read_from_stream(dut.output, extract="last"))
if i % 10 == 0:
yield from do_nothing()
self.assertEqual(last_count, 10)
platform = SimPlatform()
platform.add_sim_clock("sync", 100e6)
platform.add_process(writer, "sync")
platform.add_process(reader, "sync")
platform.sim(dut)
def test_basic(self):
platform = SimPlatform()
m = Module()
stage1 = Signal()
stage2 = Signal()
stage3 = Signal()
end = Signal()
stage3_barrier = Signal()
with m.FSM():
with Process(m, "INITIAL", to="END") as p:
m.d.comb += stage1.eq(1)
p += process_delay(m, 10)
m.d.comb += stage2.eq(1)
p += m.If(stage3_barrier)
m.d.comb += stage3.eq(1) # this will be ignored because we jump directly to the END state
with m.State("END"):
m.d.comb += end.eq(1)
def testbench():
self.assertEqual(1, (yield stage1))
yield from do_nothing(10)
self.assertEqual(0, (yield stage1))
self.assertEqual(1, (yield stage2))
yield stage3_barrier.eq(1)
yield
yield
self.assertEqual(1, (yield end))
platform.add_sim_clock("sync", 100e6)
platform.sim(m, testbench)
def test_long_fifo(self):
platform = SimPlatform()
input_stream = PacketizedStream(32)
dut = LastWrapper(input_stream, lambda i: BufferedSyncStreamFIFO(i, 200), last_rle_bits=10)
random.seed(0)
test_packets = [
[random.randint(0, 2**32) for _ in range(12)],
[random.randint(0, 2**32) for _ in range(24)],
[random.randint(0, 2**32) for _ in range(1)],
[random.randint(0, 2**32) for _ in range(1000)],
[random.randint(0, 2**32) for _ in range(1000)],
[random.randint(0, 2 ** 32) for _ in range(12)],
[random.randint(0, 2 ** 32) for _ in range(1000)],
]
def writer_process():
for packet in test_packets:
yield from write_packet_to_stream(input_stream, packet)
platform.add_process(writer_process, "sync")
def reader_process():
read_packets = []
while len(read_packets) < len(test_packets):
read = (yield from read_packet_from_stream(dut.output))
read_packets.append(read)
print([len(p) for p in read_packets])
self.assertEqual(read_packets, test_packets)
platform.add_process(reader_process, "sync")
platform.add_sim_clock("sync", 100e6)
platform.sim(dut)
def test_lp_link(self):
# in this test, we connect two DPhy lanes together and test if they can talk to each other by
# sending packets in alternating directions.
platform = SimPlatform()
m = Module()
a = m.submodules.a = DPhyDataLane(TristateIo(2),
TristateDdrIo(2),
initial_driving=True,
can_lp=True)
b = m.submodules.b = DPhyDataLane(TristateIo(2),
TristateDdrIo(2),
initial_driving=False,
can_lp=True)
with m.If(a.lp_pins.oe):
m.d.comb += b.lp_pins.i.eq(a.lp_pins.o)
with m.If(b.lp_pins.oe):
m.d.comb += a.lp_pins.i.eq(b.lp_pins.o)
packets = [
[1, 37, 254],
[1, 37, 254],
]
def writer():
for packet in packets:
yield from write_packet_to_stream(a.control_input,
packet,
timeout=400)
yield from write_packet_to_stream(a.control_input, [0x0],
timeout=400)
yield from write_packet_to_stream(b.control_input,
packet,
timeout=400)
yield from write_packet_to_stream(b.control_input, [0x0],
timeout=400)
yield Passive()
while True:
yield
platform.add_process(writer, "sync")
def reader():
for packet in packets:
self.assertEqual(packet, (yield from read_packet_from_stream(
b.control_output, timeout=400)))
self.assertEqual(packet, (yield from read_packet_from_stream(
a.control_output, timeout=400)))
platform.add_process(reader, "sync")
platform.add_sim_clock("sync", 30e6)
platform.sim(m)
def test_basic(self):
platform = SimPlatform()
axi = AxiEndpoint(addr_bits=32, data_bits=64, lite=False, id_bits=12)
data_stream = BasicStream(64)
address_stream = BasicStream(32)
write_sequence = [
(0, 1),
(0, 2),
(0, 3),
(0, 4),
(1, 5),
(2, 6),
*[(a, a) for a in range(10, 1000, 8)],
(1000, 1),
(1000, 2),
(1000, 3),
(1000, 4),
(1001, 5),
(1002, 6),
]
golden_memory = {}
for addr, data in write_sequence:
golden_memory[addr] = data
dut = AxiWriter(address_stream, data_stream, axi)
def write_address_process():
for addr, data in write_sequence:
yield from write_to_stream(address_stream, payload=addr)
platform.add_process(write_address_process, "sync")
def write_data_process():
for addr, data in write_sequence:
yield from write_to_stream(data_stream, payload=data)
platform.add_process(write_data_process, "sync")
def axi_answer_process():
memory = {}
while len(memory) < len(golden_memory):
# print("m", len(memory), memory)
written, accepted = (yield from answer_write_burst(axi))
print("w", len(written), written)
memory.update(written)
self.assertEqual(golden_memory, memory)
platform.add_process(axi_answer_process, "sync")
platform.add_sim_clock("sync", 100e6)
platform.sim(dut)
def test_roundtrip(self):
# connect a tmds encoder to a tmds decoder and verify that we receive the characters we have sent.
platform = SimPlatform()
m = Module()
data = Signal(8)
control = Signal(2)
data_enable = Signal(8)
encoder = m.submodules.encoder = TmdsEncoder(data, control, data_enable)
decoder = m.submodules.decoder = TmdsDecoder(encoder.out)
random.seed(0)
test_sequence = [10, *[random.randrange(0, 255 + 4) for _ in range(0, 1000)]]
def writer():
for x in test_sequence:
if x < 256:
yield data.eq(x)
yield data_enable.eq(1)
else:
yield data_enable.eq(0)
yield control.eq(x >> 8)
yield
platform.add_process(writer, "sync")
def reader():
active = False
seq = [*test_sequence]
while len(seq):
x = seq[0]
if active:
seq.pop(0)
if active:
if x < 256:
self.assertEqual(x, (yield data))
self.assertEqual(1, (yield data_enable))
else:
self.assertEqual(0, (yield data_enable))
self.assertEqual(x >> 8, (yield control))
elif (yield data) == x:
active = True
seq.pop(0)
yield
platform.add_process(reader, "sync")
platform.add_sim_clock("sync", 100e6)
platform.sim(m)
def test_basic(self):
platform = SimPlatform()
memory = {i: i + 100 for i in range(1000)}
read_sequence = [
0,
100,
108,
116,
2,
7,
*[i + 100 for i in range(0, 400, 8)],
0,
100,
108,
116,
2,
7,
]
golden_read_result = [memory[addr] for addr in read_sequence]
axi = AxiEndpoint(addr_bits=32, data_bits=64, lite=False, id_bits=12)
address_stream = BasicStream(32)
dut = AxiReader(address_stream, axi)
def write_address_process():
for addr in read_sequence:
yield from write_to_stream(address_stream, payload=addr)
platform.add_process(write_address_process, "sync")
def read_data_process():
read_result = []
while len(read_result) < len(golden_read_result):
read = yield from read_from_stream(dut.output)
read_result.append(read)
self.assertEqual(read_result, golden_read_result)
platform.add_process(read_data_process, "sync")
def axi_answer_process():
yield Passive()
while True:
yield from answer_read_burst(axi, memory)
platform.add_process(axi_answer_process, "sync")
platform.add_sim_clock("sync", 100e6)
platform.sim(dut)
def test_full_stack(self):
platform = SimPlatform()
m = Module()
source = m.submodules.source = GradientDemoVideoSource(direction_y=False, divider=2, width=10, height=10)
dsi_protocol = m.submodules.dsi_protocol = ImageStream2Dsi(source.output, num_lanes=2, image_width=10)
dsi_phy = m.submodules.dsi_phy = DsiPhy(("mipi", 0), num_lanes=2, ddr_domain="ddr", ck_domain="ddr")
m.d.comb += dsi_phy.hs_input.connect_upstream(dsi_protocol.output)
def testbench():
yield from do_nothing(100000)
platform.add_sim_clock("sync", 100e6)
platform.add_sim_clock("ddr", 100e6)
platform.sim(m, testbench)
def test_smoke(self):
m = Module()
platform = SimPlatform()
platform.add_sim_clock("sync", 50e6)
platform.add_sim_clock("ft601", 100e6)
ft601 = Ft601FakeResource()
stream_counter = m.submodules.stream_counter = CounterStreamSource(32, count_if_not_ready=True)
m.submodules.dut = FT601StreamSink(ft601, stream_counter.output)
def testbench():
read = []
for i in range(3):
yield ft601.txe.eq(1)
written = 0
began = False
while True:
if not began:
if (yield ft601.write):
began = True
if began:
if (yield ft601.write):
written += 1
read.append((yield ft601.data.o))
else:
yield ft601.txe.eq(0)
break
if written == 2048:
yield ft601.txe.eq(0)
break
yield
yield
assert written == 2048
for i in range(200):
yield
assert (yield ft601.write) == 0, "write was high in idle cycle {}".format(i)
# validate the received data
print(read)
last = 0
for v in read:
assert v == last
last += 1
import sys
sys.setrecursionlimit(1500) # this test compiles a rather large memory and fails with the standard recursion limit
platform.sim(m, (testbench, "ft601"))
def check_non_moving_xy(self,
transformer_function,
crop_top=0,
crop_left=0,
crop_bottom=0,
crop_right=0):
m = Module()
width, height = 9, 9
input = ImageStream(32)
transformer = m.submodules.transformer = ImageConvoluter(
input, transformer_function, width, height)
def write_process():
testdata = [[x * y for x in range(width)] for y in range(height)]
yield from write_frame_to_stream(input, testdata, pause=True)
yield from write_frame_to_stream(input, testdata, pause=True)
yield from write_frame_to_stream(input, testdata, pause=True)
yield Passive()
while True:
yield from write_to_stream(input,
line_last=0,
frame_last=0,
payload=0)
def read_process():
(yield from read_frame_from_stream(transformer.output, pause=True))
first = crop((yield from read_frame_from_stream(transformer.output,
pause=True)),
left=crop_left,
right=crop_right,
bottom=crop_bottom,
top=crop_top)
second = crop(
(yield from read_frame_from_stream(transformer.output,
pause=True)),
left=crop_left,
right=crop_right,
bottom=crop_bottom,
top=crop_top)
self.assertEqual(first, second)
platform = SimPlatform()
platform.add_sim_clock("sync", 100e6)
platform.add_process(write_process, "sync")
platform.sim(m, read_process)
def test_gearbox_8_to_4_last(self):
input = PacketizedStream(8)
dut = StreamGearbox(input, 4)
def writer():
yield from write_to_stream(input, payload=0b00_10_00_01, last=1)
yield from write_to_stream(input, payload=0b10_00_01_00, last=0)
def reader():
self.assertEqual((yield from read_from_stream(dut.output, extract=("payload", "last"))), (0b0001, 0))
self.assertEqual((yield from read_from_stream(dut.output, extract=("payload", "last"))), (0b0010, 1))
self.assertEqual((yield from read_from_stream(dut.output, extract=("payload", "last"))), (0b0100, 0))
self.assertEqual((yield from read_from_stream(dut.output, extract=("payload", "last"))), (0b1000, 0))
platform = SimPlatform()
platform.add_sim_clock("sync", 100e6)
platform.add_process(writer, "sync")
platform.add_process(reader, "sync")
platform.sim(dut)
def check_fifo_basic(self, fifo_generator):
input = BasicStream(32)
fifo = fifo_generator(input, 1024)
def testbench():
for i in range(10):
yield from write_to_stream(input, payload=i)
# async fifos need some time due to cdc
yield from do_nothing()
assert (yield fifo.r_level) == 10
for i in range(10):
assert (yield from read_from_stream(fifo.output)) == i, "read data doesnt match written data"
platform = SimPlatform()
platform.add_sim_clock("sync", 100e6)
platform.sim(fifo, testbench)
def test_hello_world(self):
platform = SimPlatform()
m = Module()
input = PacketizedStream(8)
input_data = "hello, world :)"
distribution = defaultdict(lambda: 0)
for c in input_data:
distribution[ord(c)] += 1
huffman = m.submodules.huffman = HuffmanEncoder(input, distribution)
def write_process():
for i, c in enumerate(input_data):
yield from write_to_stream(input,
payload=ord(c),
last=(i == len(input_data) - 1))
def read_process():
read = ""
while True:
data, length, last = (yield from read_from_stream(
huffman.output,
extract=("payload", "current_width", "last")))
bitstring = "{:0255b}".format(data)[::-1][:length]
read += bitstring
if last:
break
print(read)
decode_iter = bitarray(read).iterdecode(
{k: bitarray(v[::-1])
for k, v in huffman.table.items()})
decoded = ""
try:
for c in decode_iter:
decoded += chr(c)
except ValueError: # Decoding may not finish with the byte boundary
pass
self.assertEqual(input_data, decoded)
platform.add_sim_clock("sync", 100e6)
platform.add_process(write_process, "sync")
platform.sim(m, read_process)
def check_output_stable(self, debayerer_gen):
platform = SimPlatform()
m = Module()
input = ImageStream(8)
transformer = m.submodules.transformer = debayerer_gen(input)
image = imageio.imread(join(dirname(__file__), "test_bayer.png"))
def write_process():
yield from write_frame_to_stream(input, image, pause=False)
yield from write_frame_to_stream(input, image, pause=False)
yield from write_frame_to_stream(input, image, pause=False)
yield Passive()
while True:
yield from write_to_stream(input,
line_last=0,
frame_last=0,
payload=0)
def read_process():
(yield from read_frame_from_stream(transformer.output,
timeout=1000,
pause=False))
first = crop(
to_8bit_rgb((yield from
read_frame_from_stream(transformer.output,
timeout=1000,
pause=False))), 1, 1, 1, 1)
second = crop(
to_8bit_rgb((yield from
read_frame_from_stream(transformer.output,
timeout=1000,
pause=False))), 1, 1, 1, 1)
imageio.imsave(platform.output_filename_base + "_first.png", first)
imageio.imsave(platform.output_filename_base + "_second.png",
second)
self.assertEqual(first, second)
platform.add_sim_clock("sync", 100e6)
platform.add_process(write_process, "sync")
platform.sim(m, read_process)
def check_hispi_lane_manager(self, datafile):
platform = SimPlatform()
input_data = Signal(12)
dut = LaneManager(input_data)
def testbench():
def lane_n_generator(n):
with lzma.open(join(dirname(__file__), datafile), "r") as f:
for line in f:
line = line.replace(b" ", b"")
for i in range(12):
val = "0" if line[i + (n * 12)] == ord("0") else "1"
yield val
generator = lane_n_generator(0)
last_valid = 0
line_ctr = 0
for i in range(200000):
try:
if (yield dut.do_bitslip):
next(generator)
word = int("".join(reversed([next(generator) for _ in range(12)])),
2) # TODO: figure out, how this reversed() affects the real world
yield input_data.eq(word)
except RuntimeError: # this is raised when we are done instead of StopIteration
break
if (last_valid == 0) and ((yield dut.output.valid) == 1):
last_valid = 1
line_ctr = 0
elif (last_valid == 1) and ((yield dut.output.valid) == 1):
line_ctr += 1
elif (last_valid == 1) and ((yield dut.output.valid) == 0):
last_valid = 0
assert (line_ctr + 1) * 4 == 2304
yield
assert (yield dut.is_aligned) == 1, "dut is not aligned"
platform.add_sim_clock("sync", 100e6)
platform.sim(dut, testbench)
def test_hs_link(self):
platform = SimPlatform()
m = Module()
dut = m.submodules.dut = DPhyDataLane(TristateIo(2),
TristateDdrIo(2),
initial_driving=True,
ddr_domain="hs")
ddr = m.submodules.ddr = SimDdr(dut.hs_pins, domain="ddr")
packets = [[0x13, 0x00]]
def writer():
for packet in packets:
yield from write_packet_to_stream(dut.hs_input,
packet,
timeout=400)
yield from do_nothing(400)
platform.add_process(writer, "sync")
# TODO: actual testing
platform.add_sim_clock("sync", 30e6)
platform.add_sim_clock("hs", 15e6)
platform.add_sim_clock("ddr", 30e6)
platform.sim(m)
def check_move_transformer(self,
transform_xy,
testdata,
testdata_transformed,
crop_top=0,
crop_left=0,
crop_bottom=0,
crop_right=0):
m = Module()
tx, ty = transform_xy
def transformer_function(x, y, image):
return image[x + tx, y + ty]
input = ImageStream(32)
transformer = m.submodules.transformer = ImageConvoluter(
input, transformer_function, 10, 10)
def write_process():
yield from write_frame_to_stream(input, testdata, pause=True)
yield Passive()
while True:
yield from write_to_stream(input,
line_last=0,
frame_last=0,
payload=0)
def read_process():
self.assertEqual(
crop((yield from read_frame_from_stream(transformer.output,
pause=True)),
left=crop_left,
right=crop_right,
bottom=crop_bottom,
top=crop_top), testdata_transformed)
platform = SimPlatform()
platform.add_sim_clock("sync", 100e6)
platform.add_process(write_process, "sync")
platform.sim(m, read_process)
def check_multistage(self, n):
image = imageio.imread(join(dirname(__file__), "che_64.png"))
h, w = image.shape
platform = SimPlatform()
m = Module()
input = ImageStream(8)
wavelet = m.submodules.wavelet = MultiStageWavelet2D(input, w, h, stages=n)
def write_process():
yield from write_frame_to_stream(input, image, pause=False, timeout=10000)
yield Passive()
while True:
yield from write_frame_to_stream(input, image, pause=False, timeout=10000)
platform.add_process(write_process, "sync")
fifo_levels = defaultdict(lambda: defaultdict(int))
def find_maximum_fifo_level():
def find_max_levels(wavelet, level=1):
for i, fifo in enumerate(wavelet.fifos):
current_level = yield fifo.r_level
fifo_levels[level][i] = max(current_level, fifo_levels[level][i])
if hasattr(wavelet, 'next_stage'):
yield from find_max_levels(wavelet.next_stage, level + 1)
yield Passive()
while True:
yield from find_max_levels(wavelet)
yield
platform.add_process(find_maximum_fifo_level, "sync")
def read_process():
for i in range(2):
image = (yield from read_frame_from_stream(wavelet.output, timeout=1000, pause=False))
imageio.imsave(platform.output_filename_base + str(i) + ".png", image)
platform.add_process(read_process, "sync")
platform.add_sim_clock("sync", 100e6)
platform.sim(m)
print("fifo levels:", list(fifo_levels.items()))
def test_hello_world_bit_stuffing(self):
platform = SimPlatform()
m = Module()
input = PacketizedStream(8)
input_data = "hello, world :)"
distribution = defaultdict(lambda: 0)
for c in input_data:
distribution[ord(c)] += 1
huffman = m.submodules.huffman = HuffmanEncoder(input, distribution)
bit_stuffing = m.submodules.bit_stuffing = BitStuffer(
huffman.output, 8)
def write_process():
for i, c in enumerate(input_data):
yield from write_to_stream(input,
payload=ord(c),
last=(i == len(input_data) - 1))
def read_process():
read = []
while True:
payload, last = (yield from
read_from_stream(bit_stuffing.output,
extract=("payload", "last")))
read.append("{:08b}".format(payload))
if last:
break
read_bitarray = "".join(x[::-1] for x in read)
print(read_bitarray)
decode_iter = bitarray(read_bitarray).iterdecode(
{k: bitarray(v[::-1])
for k, v in huffman.table.items()})
for c, expected in zip(decode_iter, input_data):
self.assertEqual(chr(c), expected)
platform.add_sim_clock("sync", 100e6)
platform.add_process(write_process, "sync")
platform.sim(m, read_process)
def test_PacketizedStream2ImageStream(self):
platform = SimPlatform()
input_stream = PacketizedStream(32)
dut = PacketizedStream2ImageStream(input_stream, width=10)
def write_process():
for frame in range(10):
yield from write_packet_to_stream(input_stream,
[0 for _ in range(100)])
platform.add_process(write_process, "sync")
def read_process():
for frame in range(10):
frame = yield from read_frame_from_stream(dut.output)
self.assertEqual(len(frame), 10)
self.assertTrue(all(len(l) == 10 for l in frame))
platform.add_process(read_process, "sync")
platform.add_sim_clock("sync", 100e6)
platform.sim(dut)
def test_gearbox_3_to_7(self):
input = BasicStream(3)
dut = StreamGearbox(input, 7)
def writer():
yield from write_to_stream(input, payload=0b001)
yield from write_to_stream(input, payload=0b010)
yield from write_to_stream(input, payload=0b100)
yield from write_to_stream(input, payload=0b011)
yield from write_to_stream(input, payload=0b110)
yield from write_to_stream(input, payload=0b111)
yield from write_to_stream(input, payload=0b000)
def reader():
self.assertEqual((yield from read_from_stream(dut.output)), 0b0_010_001)
self.assertEqual((yield from read_from_stream(dut.output)), 0b10_011_10)
self.assertEqual((yield from read_from_stream(dut.output)), 0b000_111_1)
platform = SimPlatform()
platform.add_sim_clock("sync", 100e6)
platform.add_process(writer, "sync")
platform.add_process(reader, "sync")
platform.sim(dut)
def test_gearbox(input_width, output_width):
input = PacketizedStream(input_width)
m = Module()
fifo_in = m.submodules.fifo_in = BufferedSyncStreamFIFO(input, 100)
gearbox = m.submodules.gearbox = StreamGearbox(fifo_in.output, output_width)
fifo_out = m.submodules.fifo_out = BufferedSyncStreamFIFO(gearbox.output, 100)
input_data, output_data = gold_gen(input_width, output_width)
def writer():
for v in input_data:
yield from write_to_stream(input, payload=v)
def reader():
for i, v in enumerate(output_data):
read = (yield from read_from_stream(fifo_out.output))
self.assertEqual(read, v)
platform = SimPlatform()
platform.add_sim_clock("sync", 100e6)
platform.add_process(writer, "sync")
platform.add_process(reader, "sync")
platform.sim(m)
def test_dont_loose_data(self):
input = BasicStream(16)
dut = StreamGearbox(input, 8)
def writer():
for i in range(0, 100, 2):
yield from write_to_stream(input, payload=(((i + 1) << 8) | i))
if i % 7 == 0:
yield from do_nothing()
def reader():
for i in range(100):
got = (yield from read_from_stream(dut.output, extract="payload"))
print(got)
self.assertEqual(got, i)
if i % 3 == 0:
yield from do_nothing()
platform = SimPlatform()
platform.add_sim_clock("sync", 100e6)
platform.add_process(writer, "sync")
platform.add_process(reader, "sync")
platform.sim(dut)
def test_integration(self):
plat = SimPlatform()
m = Module()
writer_axi_port, reader_axi_port = axi_ram_sim_model(plat)
input_stream = PacketizedStream(64)
writer = m.submodules.writer = DramPacketRingbufferStreamWriter(
input_stream,
base_address=0,
max_packet_size=10000,
n_buffers=4,
axi=writer_axi_port)
reader = m.submodules.reader = DramPacketRingbufferStreamReader(
writer, axi=reader_axi_port)
cpu_reader = m.submodules.cpu_reader = DramPacketRingbufferCpuReader(
writer)
def testbench():
test_packets = [[0 for _ in range(100)], [i for i in range(100)]]
for p in test_packets:
yield from write_packet_to_stream(input_stream, p)
read_packets = []
while len(read_packets) < len(test_packets):
read = yield from read_packet_from_stream(reader.output)
read_packets.append(read)
self.assertEqual(read_packets, test_packets)
self.assertEqual((yield writer.buffer_level_list[0]), 800)
self.assertEqual((yield writer.buffer_level_list[1]), 800)
self.assertEqual((yield cpu_reader.buffer0_level), 800)
self.assertEqual((yield cpu_reader.buffer1_level), 800)
plat.add_sim_clock("sync", 100e6)
plat.sim(m, testbench)
