def test_state_variables(self):
# No parameters; nothing to infer
c = Dynamics(name='cl')
self.assertEqual(len(list(c.state_variables)), 0)
# From State Assignments and Differential Equations, and Conditionals
c = Dynamics(
name='cl',
aliases=['A1:=a+e', 'B1:=a+pi+b'],
regimes=Regime('dX/dt = (6 + c + sin(d))/t',
'dV/dt = 1.0/t',
transitions=On('V>Vt', do=['X = X + f', 'V=0'])))
self.assertEqual(
set(c.state_variable_names),
set(['X', 'V']))
self.assertRaises(
NineMLUsageError,
Dynamics,
name='cl',
aliases=['A1:=a+e', 'B1:=a+pi+b'],
regimes=Regime('dX/dt = 6 + c + sin(d)',
'dV/dt = 1.0',
transitions=On('V>Vt', do=['X = X + f', 'V=0'])
),
state_variables=['X'])
# Shouldn't pick up 'e' as a parameter:
self.assertRaises(
NineMLUsageError,
Dynamics,
name='cl',
aliases=['A1:=a+e', 'B1:=a+pi+b'],
regimes=Regime('dX/dt = 6 + c + sin(d)',
'dV/dt = 1.0',
transitions=On('V>Vt', do=['X = X + f', 'V=0'])
),
state_variables=['X', 'V', 'Vt'])
c = Dynamics(name='cl',
regimes=[
Regime('dX1/dt=1/t',
name='r1',
transitions=On('X>X1', do=['X=X0'],
to='r2')),
Regime('dX1/dt=1/t',
name='r2',
transitions=On('X>X1', do=['X=X0'],
to='r3')),
Regime('dX2/dt=1/t',
name='r3',
transitions=On('X>X1', do=['X=X0'],
to='r4')),
Regime('dX2/dt=1/t',
name='r4',
transitions=On('X>X1', do=['X=X0'],
to='r1'))])
self.assertEqual(set(c.state_variable_names),
set(['X1', 'X2', 'X']))
def test_event_ports(self):
# Signature: name
# No Docstring
# Check inference of output event ports:
c = Dynamics(
name='Comp1',
regimes=Regime(
transitions=[
On('V > a', do=OutputEvent('ev_port1')),
On('V > b', do=OutputEvent('ev_port1')),
On('V < c', do=OutputEvent('ev_port2')),
]
),
)
self.assertEquals(len(list(c.event_ports)), 2)
# Check inference of output event ports:
c = Dynamics(
name='Comp1',
regimes=[
Regime(name='r1',
transitions=[
On('V > a', do=OutputEvent('ev_port1'), to='r2'),
On('V < b', do=OutputEvent('ev_port2'))]),
Regime(name='r2',
transitions=[
On('V > a', do=OutputEvent('ev_port2'), to='r1'),
On('V < b', do=OutputEvent('ev_port3'))])
]
)
self.assertEquals(len(list(c.event_ports)), 3)
# Check inference of output event ports:
c = Dynamics(
name='Comp1',
regimes=[
Regime(name='r1',
transitions=[
On('spikeinput1', do=[]),
On('spikeinput2', do=OutputEvent('ev_port2'),
to='r2')]),
Regime(name='r2',
transitions=[
On('V > a', do=OutputEvent('ev_port2')),
On('spikeinput3', do=OutputEvent('ev_port3'),
to='r1')])
]
)
self.assertEquals(len(list(c.event_ports)), 5)
def test_parameters(self):
# Signature: name
# No Docstring
# No parameters; nothing to infer
c = Dynamics(name='cl')
self.assertEqual(len(list(c.parameters)), 0)
# Mismatch between inferred and actual parameters
self.assertRaises(
NineMLUsageError,
Dynamics, name='cl', parameters=['a'])
# Single parameter inference from an alias block
c = Dynamics(name='cl', aliases=['A1:=a'])
self.assertEqual(len(list(c.parameters)), 1)
self.assertEqual(list(c.parameters)[0].name, 'a')
# More complex inference:
c = Dynamics(name='cl', aliases=['A1:=a+e', 'B1:=a+pi+b'],
constants=[Constant('pi', 3.141592653589793)])
self.assertEqual(len(list(c.parameters)), 3)
self.assertEqual(sorted([p.name for p in c.parameters]),
['a', 'b', 'e'])
# From State Assignments and Differential Equations, and Conditionals
c = Dynamics(name='cl',
aliases=['A1:=a+e', 'B1:=a+pi+b'],
regimes=Regime('dX/dt = (6 + c + sin(d))/t',
'dV/dt = 1.0/t',
transitions=On('V>Vt',
do=['X = X + f', 'V=0'])),
constants=[Constant('pi', 3.1415926535)])
self.assertEqual(len(list(c.parameters)), 7)
self.assertEqual(
sorted([p.name for p in c.parameters]),
['Vt', 'a', 'b', 'c', 'd', 'e', 'f'])
self.assertRaises(
NineMLUsageError,
Dynamics,
name='cl',
aliases=['A1:=a+e', 'B1:=a+pi+b'],
regimes=Regime('dX/dt = 6 + c + sin(d)',
'dV/dt = 1.0',
transitions=On('V>Vt', do=['X = X + f', 'V=0'])
),
parameters=['a', 'b', 'c'])
def test_good_model(self):
Dynamics(name='A',
aliases=['A1:=P1 * SV2', 'A2 := ARP1 + SV2', 'A3 := SV1'],
state_variables=[
StateVariable('SV1', dimension=un.voltage),
StateVariable('SV2', dimension=un.current)
],
regimes=[
Regime('dSV1/dt = -SV1 / P2',
'dSV2/dt = A3 / ARP2 + SV2 / P2',
transitions=[
On('SV1 > P3', do=[OutputEvent('emit')]),
On('spikein', do=[OutputEvent('emit')])
],
name='R1'),
Regime(name='R2',
transitions=On('(SV1 > C1) & (SV2 < P4)', to='R1'))
],
analog_ports=[
AnalogReceivePort('ARP1', dimension=un.current),
AnalogReceivePort('ARP2',
dimension=(un.resistance * un.time)),
AnalogSendPort('A1', dimension=un.voltage * un.current),
AnalogSendPort('A2', dimension=un.current)
],
parameters=[
Parameter('P1', dimension=un.voltage),
Parameter('P2', dimension=un.time),
Parameter('P3', dimension=un.voltage),
Parameter('P4', dimension=un.current)
],
constants=[Constant('C1', value=1.0, units=un.mV)])
def test_output_filtering(self):
"""
Tests whether the 'outputs' argument is able to filter (presumably)
unconnected nonlinear mappings from inputs and states to analog send
ports
"""
e = Dynamics(name='E',
regimes=[
Regime('dSV1/dt = -SV1 / P1',
'dSV2/dt = -SV2 / P1 + ARP1 * P2',
name='R1')
],
aliases=['A1:=SV1 * C1', 'A2:=SV1 * SV2'],
analog_ports=[
AnalogReceivePort('ARP1', dimension=un.per_time),
AnalogSendPort('A1', dimension=un.current),
AnalogSendPort('A2', dimension=un.dimensionless)
],
parameters=[
Parameter('P1', dimension=un.time),
Parameter('P2', dimension=un.dimensionless)
],
constants=[Constant('C1', 10, units=un.mA)])
self.assertFalse(e.is_linear())
self.assertTrue(e.is_linear(outputs=['A1']))
def test_regime_aliases(self):
a = Dynamics(
name='a',
aliases=[Alias('A', '4/t')],
regimes=[
Regime('dX/dt=1/t + A',
name='r1',
transitions=On('X>X1', do=['X=X0'], to='r2')),
Regime('dX/dt=1/t + A',
name='r2',
transitions=On('X>X1', do=['X=X0'],
to='r1'),
aliases=[Alias('A', '8 / t')])])
self.assertEqual(a.regime('r2').alias('A'), Alias('A', '8 / t'))
self.assertRaises(
NineMLUsageError,
Dynamics,
name='a',
regimes=[
Regime('dX/dt=1/t + A',
name='r1',
transitions=On('X>X1', do=['X=X0'], to='r2')),
Regime('dX/dt=1/t + A',
name='r2',
transitions=On('X>X1', do=['X=X0'],
to='r1'),
aliases=[Alias('A', '8 / t')])])
document = Document()
a_xml = a.serialize(format='xml', version=1, document=document)
b = Dynamics.unserialize(a_xml, format='xml', version=1,
document=Document(un.dimensionless.clone()))
self.assertEqual(a, b,
"Dynamics with regime-specific alias failed xml "
"roundtrip:\n{}".format(a.find_mismatch(b)))
def test_ports(self):
# Signature: name
# Return an iterator over all the port (Event & Analog) in the
# component
# from nineml.abstraction.component.componentqueryer import
# ComponentClassQueryer
c = Dynamics(
name='Comp1',
regimes=[
Regime(name='r1',
transitions=[
On('spikeinput1', do=[]),
On('spikeinput2', do=OutputEvent('ev_port2'),
to='r2')]),
Regime(name='r2',
transitions=[
On('V > a', do=OutputEvent('ev_port2')),
On('spikeinput3', do=OutputEvent('ev_port3'),
to='r1')])
],
aliases=['A1:=0', 'C:=0'],
analog_ports=[AnalogSendPort('A1'), AnalogReceivePort('B'),
AnalogSendPort('C')]
)
ports = list(list(c.ports))
port_names = [p.name for p in ports]
self.assertEquals(len(port_names), 8)
self.assertEquals(set(port_names),
set(['A1', 'B', 'C', 'spikeinput1', 'spikeinput2',
'spikeinput3', 'ev_port2', 'ev_port3'])
)
def test_nonlinear_state_assignment_in_onevent(self):
"""Test that nonlinear state assignements in on events"""
g = Dynamics(name='G',
regimes=[
Regime('dSV1/dt = -SV1 / P1',
'dSV2/dt = -SV2 / P1 + ARP1 * P2',
name='R1',
transitions=[
OnEvent('ERP1',
state_assignments=[
StateAssignment(
'SV2', 'SV2 + A2')
])
])
],
aliases=['A1:=SV1 * C1', 'A2:=P3 * P4 / ADP1'],
analog_ports=[
AnalogReceivePort('ARP1', dimension=un.per_time),
AnalogReducePort('ADP1',
operator='+',
dimension=un.dimensionless),
AnalogSendPort('A1', dimension=un.current),
AnalogSendPort('A2', dimension=un.dimensionless)
],
event_ports=[EventReceivePort('ERP1')],
parameters=[
Parameter('P1', dimension=un.time),
Parameter('P2', dimension=un.dimensionless),
Parameter('P3', dimension=un.resistance),
Parameter('P4', dimension=un.conductance)
],
constants=[Constant('C1', 10, units=un.nA)])
self.assertFalse(g.is_linear())
def test_regime(self):
# Signature: name(self, name=None)
# Find a regime in the component by name
# from nineml.abstraction.component.componentqueryer import
# ComponentClassQueryer
c = Dynamics(name='cl',
regimes=[
Regime('dX/dt=1/t',
name='r1',
transitions=On('X>X1', do=['X=X0'],
to='r2')),
Regime('dX/dt=1/t',
name='r2',
transitions=On('X>X1', do=['X=X0'],
to='r3')),
Regime('dX/dt=1/t',
name='r3',
transitions=On('X>X1', do=['X=X0'],
to='r4')),
Regime('dX/dt=1/t',
name='r4',
transitions=On('X>X1', do=['X=X0'],
to='r1'))])
self.assertEqual(c.regime(name='r1').name, 'r1')
self.assertEqual(c.regime(name='r2').name, 'r2')
self.assertEqual(c.regime(name='r3').name, 'r3')
self.assertEqual(c.regime(name='r4').name, 'r4')
def setUp(self):
self.parameters = ['P4', 'P1', 'P3', 'P5', 'P2']
self.state_variables = ['SV3', 'SV5', 'SV4', 'SV2', 'SV1']
self.regimes = ['R2', 'R3', 'R1']
self.time_derivatives = {
'R1': ['SV5', 'SV1', 'SV4', 'SV3', 'SV2'],
'R2': ['SV2', 'SV4'],
'R3': ['SV4', 'SV2', 'SV1']
}
self.aliases = ['A4', 'A3', 'A1', 'A2']
# Create a dynamics object with elements in a particular order
self.d = Dynamics(
name='d',
parameters=[Parameter(p) for p in self.parameters],
state_variables=[StateVariable(sv) for sv in self.state_variables],
regimes=[
Regime(name=r,
time_derivatives=[
TimeDerivative(td, '{}/t'.format(td))
for td in self.time_derivatives[r]
],
transitions=[
OnCondition('SV1 > P5',
target_regime_name=self.regimes[
self.regimes.index(r) - 1])
]) for r in self.regimes
],
aliases=[
Alias(a, 'P{}'.format(i + 1))
for i, a in enumerate(self.aliases)
])
def test_standardize_units_ninemlruntimeerror2(self):
"""
line #: 268
message: Name of dimension '{}' conflicts with existing object of
differring value or type '{}' and '{}'
"""
a = Dynamics(
name='A',
parameters=[
Parameter('P1', dimension=un.Dimension(name='D', t=1))],
regime=Regime(name='default'),
aliases=['A1 := P1 * 2'])
b = Dynamics(
name='B',
parameters=[
Parameter('P1', dimension=un.Dimension(name='D', l=1))],
regime=Regime(name='default'),
aliases=['A1 := P1 * 2'])
self.assertRaises(
NineMLUsageError,
Document, a, b)
def build_network(sim, order=1000, epsilon=0.1, delay=1.5, J=0.1, theta=20.0,
tau=20.0, tau_syn=0.1, tau_refrac=2.0, v_reset=10.0,
R=1.5, g=5, eta=2, seed=None):
NE = 4 * order
NI = 1 * order
CE = int(epsilon * NE) # number of excitatory synapses per neuron
CI = int(epsilon * NI) # number of inhibitory synapses per neuron
CMem = tau/R
J_unit = psp_height(tau, R, tau_syn)
J_ex = J / J_unit
J_in = -g * J_ex
nu_th = theta / (J_ex * CE * R * tau_syn)
nu_ex = eta * nu_th
p_rate = 1000.0 * nu_ex * CE
assert seed is not None
rng = NumpyRNG(seed)
neuron_params = {
"nrn_tau": tau,
"nrn_v_threshold": theta,
"nrn_refractory_period": tau_refrac,
"nrn_v_reset": v_reset,
"nrn_R": R,
"syn_tau": tau_syn
}
celltype = Dynamics(name='iaf',
subnodes={'nrn': read("sources/BrunelIaF.xml")['BrunelIaF'],
'syn': read("sources/AlphaPSR.xml")['AlphaPSR']})
celltype.connect_ports('syn.i_synaptic', 'nrn.i_synaptic')
exc = sim.Population(NE, nineml_cell_type('BrunelIaF', celltype, {'syn': 'syn_weight'})(**neuron_params))
inh = sim.Population(NI, nineml_cell_type('BrunelIaF', celltype, {'syn': 'syn_weight'})(**neuron_params))
all = exc + inh
all.initialize(v=RandomDistribution('uniform', (0.0, theta), rng=rng))
stim = sim.Population(NE + NI, nineml_cell_type('Poisson', read("sources/Poisson.xml")['Poisson'], {})(rate=p_rate))
print("Connecting network")
exc_synapse = sim.StaticSynapse(weight=J_ex, delay=delay)
inh_synapse = sim.StaticSynapse(weight=J_in, delay=delay)
input_connections = sim.Projection(stim, all, sim.OneToOneConnector(), exc_synapse, receptor_type="syn")
exc_connections = sim.Projection(exc, all, sim.FixedNumberPreConnector(n=CE), exc_synapse, receptor_type="syn") # check is Pre not Post
inh_connections = sim.Projection(inh, all, sim.FixedNumberPreConnector(n=CI), inh_synapse, receptor_type="syn")
return stim, exc, inh
def test_aliases_map(self):
# Signature: name
# Forwarding function to self.dynamics.alias_map
self.assertEqual(
Dynamics(name='C1')._aliases, {}
)
c1 = Dynamics(name='C1', aliases=['A:=3'])
self.assertEqual(c1.alias('A').rhs_as_python_func(), 3)
self.assertEqual(len(c1._aliases), 1)
c2 = Dynamics(name='C1', aliases=['A:=3', 'B:=5'])
self.assertEqual(c2.alias('A').rhs_as_python_func(), 3)
self.assertEqual(c2.alias('B').rhs_as_python_func(), 5)
self.assertEqual(len(c2._aliases), 2)
c3 = Dynamics(name='C1', aliases=['C:=13', 'Z:=15'])
self.assertEqual(c3.alias('C').rhs_as_python_func(), 13)
self.assertEqual(c3.alias('Z').rhs_as_python_func(), 15)
self.assertEqual(len(c3._aliases), 2)
def setUp(self):
self.a = Dynamics(
name='A',
aliases=[
'A1 := P1 / P2', 'A2 := ARP2 + P3', 'A3 := P4 * P5',
'A4 := 1 / (P2 * P6) + ARP3', 'A5 := P7 * P8', 'A6 := P9/P10'
],
regimes=[
Regime('dSV1/dt = -A1 / A2',
('dSV2/dt = C1 * SV2 ** 2 + C2 * SV2 + C3 + SV3 + '
'ARP4 / P11'),
'dSV3/dt = P12*(SV2*P13 - SV3)',
name='R1')
],
state_variables=[
StateVariable('SV1', dimension=un.dimensionless),
StateVariable('SV2', dimension=un.voltage),
StateVariable('SV3', dimension=old_div(un.voltage, un.time))
],
analog_ports=[
AnalogReceivePort('ARP1', dimension=un.resistance),
AnalogReceivePort('ARP2', dimension=un.charge),
AnalogReceivePort('ARP3', dimension=un.conductanceDensity),
AnalogReceivePort('ARP4', dimension=un.current)
],
parameters=[
Parameter('P1', dimension=un.voltage),
Parameter('P2', dimension=un.resistance),
Parameter('P3', dimension=un.charge),
Parameter('P4', dimension=old_div(un.length, un.current**2)),
Parameter('P5', dimension=old_div(un.current**2, un.length)),
Parameter('P6', dimension=un.length**2),
Parameter('P7', dimension=old_div(un.current, un.capacitance)),
Parameter('P8', dimension=un.time),
Parameter('P9',
dimension=old_div(un.capacitance, un.length**2)),
Parameter('P10',
dimension=old_div(un.conductance, un.length**2)),
Parameter('P11', dimension=un.capacitance),
Parameter('P12', dimension=un.per_time),
Parameter('P13', dimension=un.per_time)
],
constants=[
Constant('C1',
0.04,
units=(old_div(un.unitless, (un.mV * un.ms)))),
Constant('C2', 5.0, units=old_div(un.unitless, un.ms)),
Constant('C3', 140.0, units=old_div(un.mV, un.ms))
])
def test_nonlinear_function(self):
"""Nonlinear due function in SV1 T.D."""
h = Dynamics(
name='H',
regimes=[
Regime('dSV1/dt = -sin(SV1) / P1',
'dSV2/dt = -SV2 / P1 + ARP1 * P2',
name='R1')
],
analog_ports=[AnalogReceivePort('ARP1', dimension=un.per_time)],
parameters=[
Parameter('P1', dimension=un.time),
Parameter('P2', dimension=un.dimensionless)
])
self.assertFalse(h.is_linear())
def test_multi_regime_nonlinear(self):
"""Nonlinear due to multiple regimes"""
b = Dynamics(
name='B',
regimes=[
Regime('dSV1/dt = -SV1 / P1',
transitions=[OnEvent('ERP1', target_regime_name='R2')],
name='R1'),
Regime('dSV1/dt = -SV1 / P1',
transitions=[OnEvent('ERP1', target_regime_name='R1')],
name='R2')
],
event_ports=[EventReceivePort('ERP1')],
parameters=[Parameter('P1', dimension=un.time)])
self.assertFalse(b.is_linear())
def test_input_multiplication_nonlinear(self):
"""Nonlinear due to multiplication of SV1 and SV2 in SV1 T.D."""
d = Dynamics(
name='D',
regimes=[
Regime('dSV1/dt = -SV1 * SV2 / P1',
'dSV2/dt = -SV2 / P1 + ARP1 * P2',
name='R1')
],
analog_ports=[AnalogReceivePort('ARP1', dimension=un.per_time)],
parameters=[
Parameter('P1', dimension=un.time),
Parameter('P2', dimension=un.dimensionless)
])
self.assertFalse(d.is_linear())
def test_basic_linear(self):
"""A basic linear dynamics example"""
a = Dynamics(
name='A',
regimes=[
Regime('dSV1/dt = -SV1 / P1',
'dSV2/dt = -SV2 / P1 + ARP1 * P2',
name='R1')
],
analog_ports=[AnalogReceivePort('ARP1', dimension=un.per_time)],
parameters=[
Parameter('P1', dimension=un.time),
Parameter('P2', dimension=un.dimensionless)
])
self.assertTrue(a.is_linear())
def duplicate_port_name_event_analog(self):
# Check different names are OK:
Dynamics(
name='C1', aliases=['A1:=1'],
event_ports=[EventReceivePort('A')],
analog_ports=[AnalogSendPort('A')])
self.assertRaises(
NineMLUsageError,
Dynamics,
name='C1',
aliases=['A1:=1'],
event_ports=[EventReceivePort('A')],
analog_ports=[AnalogSendPort('A')]
)
def test_on_condition_state_assignment_nonlinear(self):
"""
Nonlinear due to a state assignment in on-condition (i.e. piece-wise
dynamics
"""
c = Dynamics(name='C',
regimes=[
Regime('dSV1/dt = -P1 * SV1',
transitions=[
OnCondition('SV1 > 10',
state_assignments=[
StateAssignment('SV1', 20)
])
],
name='R1')
],
parameters=[Parameter('P1', dimension=un.per_time)])
self.assertFalse(c.is_linear())
def test_transitions(self):
c = Dynamics(name='cl',
regimes=[
Regime('dX1/dt=1/t',
name='r1',
transitions=[On('X>X1', do=['X=X0'],
to='r2'),
On('X>X2', do=['X=X0'],
to='r3'), ]
),
Regime('dX1/dt=1/t',
name='r2',
transitions=On('X>X1', do=['X=X0'],
to='r3'),),
Regime('dX2/dt=1/t',
name='r3',
transitions=[On('X>X1', do=['X=X0'],
to='r4'),
On('X>X2', do=['X=X0'],
to=None)]),
Regime('dX2/dt=1/t',
name='r4',
transitions=On('X>X1', do=['X=X0'],
to=None))])
self.assertEquals(len(list(c.all_transitions())), 6)
r1 = c.regime('r1')
r2 = c.regime('r2')
r3 = c.regime('r3')
r4 = c.regime('r4')
self.assertEquals(len(list(r1.transitions)), 2)
self.assertEquals(len(list(r2.transitions)), 1)
self.assertEquals(len(list(r3.transitions)), 2)
self.assertEquals(len(list(r4.transitions)), 1)
def target_regimes(regime):
return unique_by_id(t.target_regime for t in regime.transitions)
self.assertEquals(target_regimes(r1), [r2, r3])
self.assertEquals(target_regimes(r2), [r3])
self.assertEquals(target_regimes(r3), [r3, r4])
self.assertEquals(target_regimes(r4), [r4])
def test_equals_with_annotations_ns(self):
a = Dynamics(name='D',
parameters=[Parameter('P', dimension=un.dimensionless)],
aliases=[Alias('A', 'P')])
b = a.clone()
c = a.clone()
d = a.clone()
e = a.clone()
a.parameter('P').annotations.set(('annot1', 'dummy_ns'), 'val1', 1.0)
b.parameter('P').annotations.set(('annot1', 'dummy_ns'), 'val1', 1.0)
c.parameter('P').annotations.set(('annot1', 'dummy_ns'), 'val1', 2.0)
e.parameter('P').annotations.set(('annot1', 'dummy_ns2'), 'val1', 1.0)
self.assertTrue(a.equals(b, annotations_ns=['dummy_ns']))
self.assertTrue(a.equals(c))
self.assertFalse(a.equals(c, annotations_ns=['dummy_ns']))
self.assertTrue(a.equals(d))
self.assertFalse(a.equals(d, annotations_ns=['dummy_ns']))
self.assertTrue(a.equals(e))
self.assertFalse(a.equals(e, annotations_ns=['dummy_ns']))
def test_unused_reduce_ports(self):
"""
Tests whether empty reduce ports are "closed" by inserting a zero-
valued constant in their stead
"""
test_dyn = Dynamics(
name='TestDyn',
regimes=[Regime('dSV1/dt = -P1/t + ADP1', name='r1')],
analog_ports=[AnalogReducePort('ADP1', un.per_time)],
parameters=['P1'])
test_multi = MultiDynamics(name="TestMultiDyn",
sub_components={'cell': test_dyn})
self.assert_(
Constant('ADP1__cell', 0.0,
un.per_time.origin.units) in test_multi.constants,
"Zero-valued constant wasn't inserted for unused reduce "
"port")
def setUp(self):
self.a = Dynamics(
name='A',
aliases=['A1:=P1 / P2', 'A2 := ARP2 + P3', 'A3 := P4 * P5'],
regimes=[
Regime('dSV1/dt = -A1 / A2',
aliases=[Alias('A1', 'P1 / P2 * 2')],
name='R1')
],
analog_ports=[
AnalogReceivePort('ARP1', dimension=un.resistance),
AnalogReceivePort('ARP2', dimension=un.charge)
],
parameters=[
Parameter('P1', dimension=un.voltage),
Parameter('P2', dimension=un.resistance),
Parameter('P3', dimension=un.charge),
Parameter('P4', dimension=old_div(un.length, un.current**2)),
Parameter('P5', dimension=old_div(un.current**2, un.length))
])
def test_all_expressions(self):
a = Dynamics(
name='A',
aliases=['A1:=P1 * SV2', 'A2 := ARP1 + SV2', 'A3 := SV1'],
state_variables=[
StateVariable('SV1', dimension=un.voltage),
StateVariable('SV2', dimension=un.current)],
regimes=[
Regime(
'dSV1/dt = -SV1 / P2',
'dSV2/dt = A3 / ARP2 + SV2 / P2',
transitions=[On('SV1 > P3', do=[OutputEvent('emit')]),
On('spikein', do=[OutputEvent('emit')])],
name='R1'
),
Regime(name='R2', transitions=On('(SV1 > C1) & (SV2 < P4)',
to='R1'))
],
analog_ports=[AnalogReceivePort('ARP1', dimension=un.current),
AnalogReceivePort('ARP2',
dimension=(un.resistance *
un.time)),
AnalogSendPort('A1',
dimension=un.voltage * un.current),
AnalogSendPort('A2', dimension=un.current)],
parameters=[Parameter('P1', dimension=un.voltage),
Parameter('P2', dimension=un.time),
Parameter('P3', dimension=un.voltage),
Parameter('P4', dimension=un.current)],
constants=[Constant('C1', value=1.0, units=un.mV)]
)
self.assertEqual(
set(a.all_expressions), set((
sympify('P1 * SV2'), sympify('ARP1 + SV2'), sympify('SV1'),
sympify('-SV1 / P2'), sympify('-SV1 / P2'),
sympify('A3 / ARP2 + SV2 / P2'), sympify('SV1 > P3'),
sympify('(SV1 > C1) & (SV2 < P4)'))),
"All expressions were not extracted from component class")
def test_event_send_receive_ports(self):
# Signature: name(self)
# Get the ``recv`` EventPorts
# from nineml.abstraction.component.componentqueryer import
# ComponentClassQueryer
# Check inference of output event ports:
c = Dynamics(
name='Comp1',
regimes=Regime(
transitions=[
On('in_ev1', do=OutputEvent('ev_port1')),
On('V < b', do=OutputEvent('ev_port1')),
On('V < c', do=OutputEvent('ev_port2')),
]
),
)
self.assertEquals(len(list(c.event_receive_ports)), 1)
self.assertEquals((list(list(c.event_receive_ports))[0]).name,
'in_ev1')
self.assertEquals(len(list(c.event_send_ports)), 2)
self.assertEquals(set(c.event_send_port_names),
set(['ev_port1', 'ev_port2']))
# Check inference of output event ports:
c = Dynamics(
name='Comp1',
regimes=[
Regime(name='r1',
transitions=[
On('V > a', do=OutputEvent('ev_port1'), to='r2'),
On('in_ev1', do=OutputEvent('ev_port2'))]),
Regime(name='r2',
transitions=[
On('V > a', do=OutputEvent('ev_port2'), to='r1'),
On('in_ev2', do=OutputEvent('ev_port3'))])
]
)
self.assertEquals(len(list(c.event_receive_ports)), 2)
self.assertEquals(set(c.event_receive_port_names),
set(['in_ev1', 'in_ev2']))
self.assertEquals(len(list(c.event_send_ports)), 3)
self.assertEquals(set(c.event_send_port_names),
set(['ev_port1', 'ev_port2', 'ev_port3']))
# Check inference of output event ports:
c = Dynamics(
name='Comp1',
regimes=[
Regime(name='r1',
transitions=[
On('spikeinput1', do=[]),
On('spikeinput2', do=[
OutputEvent('ev_port1'),
OutputEvent('ev_port2')], to='r2')]),
Regime(name='r2',
transitions=[
On('V > a', do=OutputEvent('ev_port2')),
On('spikeinput3', do=OutputEvent('ev_port3'),
to='r1')])
]
)
self.assertEquals(len(list(c.event_receive_ports)), 3)
self.assertEquals(set(c.event_receive_port_names),
set(['spikeinput1', 'spikeinput2', 'spikeinput3']))
self.assertEquals(len(list(c.event_send_ports)), 3)
self.assertEquals(set(c.event_send_port_names),
set(['ev_port1', 'ev_port2', 'ev_port3']))
dynA = Dynamics(name='dynA',
aliases=[
'A1:=P1 * SV2', 'A2 := ARP1 + SV2', 'A3 := SV1',
'A4 := C2 * SV1'
],
state_variables=[
StateVariable('SV1', dimension=un.voltage),
StateVariable('SV2', dimension=un.current)
],
regimes=[
Regime('dSV1/dt = -SV1 / P2',
'dSV2/dt = A3 / ARP2 + SV2 / P2',
transitions=[
On(Trigger('SV1 > P3'),
do=[OutputEvent('ESP1')]),
On('ERP1', do=[OutputEvent('ESP2')])
],
name='R1'),
Regime(name='R2',
transitions=[
OnCondition('(SV1 > C1) & (SV2 < P4)',
target_regime_name='R1')
])
],
analog_ports=[
AnalogReceivePort('ARP1', dimension=un.current),
AnalogReceivePort('ARP2',
dimension=(un.resistance * un.time)),
AnalogSendPort('A1', dimension=un.voltage * un.current),
AnalogSendPort('A2', dimension=un.current)
],
parameters=[
Parameter('P1', dimension=un.voltage),
Parameter('P2', dimension=un.time),
Parameter('P3', dimension=un.voltage),
Parameter('P4', dimension=un.current)
],
constants=[
Constant('C1', value=-71.0, units=un.mV),
Constant('C2', value=22.2, units=un.degC)
])
def get_compound_component():
"""Cannot yet be implemented in PyDSTool
"""
from nineml.abstraction.testing_utils import RecordValue
from nineml.abstraction import Dynamics, Regime, On, OutputEvent, AnalogSendPort, AnalogReducePort
emitter = Dynamics(
name='EventEmitter',
parameters=['cyclelength'],
regimes=[
Regime(transitions=On('t > tchange + cyclelength',
do=[OutputEvent('emit'), 'tchange=t'])),
])
ev_based_cc = Dynamics(
name='EventBasedCurrentClass',
parameters=['dur', 'i'],
analog_ports=[AnalogSendPort('I')],
regimes=[
Regime(transitions=[
On('inputevent', do=['I=i', 'tchange = t']),
On('t>tchange + dur', do=['I=0', 'tchange=t'])
])
])
pulsing_emitter = Dynamics(name='pulsing_cc',
subnodes={
'evs': emitter,
'cc': ev_based_cc
},
portconnections=[('evs.emit', 'cc.inputevent')])
nrn = Dynamics(
name='LeakyNeuron',
parameters=['Cm', 'gL', 'E'],
regimes=[
Regime('dV/dt = (iInj + (E-V)*gL )/Cm'),
],
aliases=['iIn := iInj'],
analog_ports=[
AnalogSendPort('V'),
AnalogReducePort('iInj', operator='+')
],
)
combined_comp = Dynamics(name='Comp1',
subnodes={
'nrn': nrn,
'cc1': pulsing_emitter,
'cc2': pulsing_emitter
},
portconnections=[('cc1.cc.I', 'nrn.iInj'),
('cc2.cc.I', 'nrn.iInj')])
combined_comp = al.flattening.flatten(combined_comp)
## records = [
## RecordValue(what='cc1_cc_I', tag='Current', label='Current Clamp 1'),
## RecordValue(what='cc2_cc_I', tag='Current', label='Current Clamp 2'),
## RecordValue(what='nrn_iIn', tag='Current', label='Total Input Current'),
## RecordValue(what='nrn_V', tag='Voltage', label='Neuron Voltage'),
## RecordValue(what='cc1_cc_tchange', tag='Tchange', label='tChange CC1'),
## RecordValue(what='cc2_cc_tchange', tag='Tchange', label='tChange CC2'),
## RecordValue(what='regime', tag='Regime', label='Regime'),
## ]
parameters = al.flattening.ComponentFlattener.flatten_namespace_dict({
'cc1.cc.i':
13.8,
'cc1.cc.dur':
10,
'cc1.evs.cyclelength':
30,
'cc2.cc.i':
20.8,
'cc2.cc.dur':
5.0,
'cc2.evs.cyclelength':
20,
'nrn.gL':
4.3,
'nrn.E':
-70
})
return combined_comp, parameters
def setUp(self):
self.a = Dynamics(name='A',
aliases=['A1:=P1', 'A2 := ARP1 + SV2', 'A3 := SV1'],
regimes=[
Regime(
'dSV1/dt = -SV1 / (P2*t)',
'dSV2/dt = SV1 / (ARP1*t) + SV2 / (P1*t)',
transitions=[
On('SV1 > P1', do=[OutputEvent('emit')]),
On('spikein', do=[OutputEvent('emit')])
],
name='R1',
),
Regime(name='R2',
transitions=On('SV1 > 1', to='R1'))
],
analog_ports=[
AnalogReceivePort('ARP1'),
AnalogReceivePort('ARP2'),
AnalogSendPort('A1'),
AnalogSendPort('A2')
],
parameters=['P1', 'P2'])
self.b = Dynamics(name='B',
aliases=[
'A1:=P1', 'A2 := ARP1 + SV2', 'A3 := SV1',
'A4 := SV1^3 + SV2^3'
],
regimes=[
Regime(
'dSV1/dt = -SV1 / (P2*t)',
'dSV2/dt = SV1 / (ARP1*t) + SV2 / (P1*t)',
'dSV3/dt = -SV3/t + P3/t',
transitions=[
On('SV1 > P1', do=[OutputEvent('emit')]),
On('spikein',
do=[
OutputEvent('emit'),
StateAssignment('SV1', 'P1')
])
],
name='R1',
),
Regime(name='R2',
transitions=[
On('SV1 > 1', to='R1'),
On('SV3 < 0.001',
to='R2',
do=[StateAssignment('SV3', 1)])
])
],
analog_ports=[
AnalogReceivePort('ARP1'),
AnalogReceivePort('ARP2'),
AnalogSendPort('A1'),
AnalogSendPort('A2'),
AnalogSendPort('A3'),
AnalogSendPort('SV3')
],
parameters=['P1', 'P2', 'P3'])
self.a_props = DynamicsProperties(name="AProps",
definition=self.a,
properties={
'P1': 1,
'P2': 2
})
self.b_props = DynamicsProperties(name="BProps",
definition=self.b,
properties={
'P1': 1,
'P2': 2,
'P3': 3
})
def test_basic_flattening(self):
c = Dynamics(name='C',
aliases=['C1:=cp1', 'C2 := cIn1', 'C3 := SV1'],
regimes=[
Regime(
'dSV1/dt = -SV1/(cp2*t)',
transitions=[
On('SV1>cp1', do=[OutputEvent('emit')]),
On('spikein',
do=[
OutputEvent('emit'),
StateAssignment('SV1', '10')
])
],
name='r1',
),
Regime(name='r2', transitions=On('SV1>1', to='r1'))
],
analog_ports=[
AnalogReceivePort('cIn1'),
AnalogReceivePort('cIn2'),
AnalogSendPort('C1'),
AnalogSendPort('C2')
],
parameters=['cp1', 'cp2'])
d = Dynamics(name='D',
aliases=['D1:=dp1', 'D2 := dIn1', 'D3 := SV1'],
regimes=[
Regime(
'dSV1/dt = -SV1/(dp2*t)',
transitions=[
On('SV1>dp1', do=[OutputEvent('emit')]),
On('spikein', do=[OutputEvent('emit')])
],
name='r1',
),
Regime(name='r2', transitions=On('SV1>1', to='r1'))
],
analog_ports=[
AnalogReceivePort('dIn1'),
AnalogReceivePort('dIn2'),
AnalogSendPort('D1'),
AnalogSendPort('D2')
],
parameters=['dp1', 'dp2'])
e = MultiDynamics(name='E',
sub_components={
'a': c,
'b': d
},
port_connections=[('a', 'C1', 'b', 'dIn1'),
('a', 'C2', 'b', 'dIn2')],
port_exposures=[('a', 'cIn1', 'ARP1'),
('a', 'cIn2', 'ARP2'),
('a', 'spikein', 'ERP1'),
('a', 'emit', 'ESP1')])
# =====================================================================
# General properties
# =====================================================================
self.assertEqual(e.name, 'E')
self.assertEqual(set(e.parameter_names),
set(['cp1__a', 'cp2__a', 'dp1__b', 'dp2__b']))
cp1 = e.parameter('cp1__a')
self.assertEqual(cp1.dimension, un.dimensionless)
self.assertEqual(set(e.analog_receive_port_names),
set(['ARP1', 'ARP2']))
arp1 = e.analog_receive_port('ARP1')
self.assertEqual(arp1.dimension, un.dimensionless)
self.assertEqual(set(e.event_receive_port_names), set(['ERP1']))
self.assertEqual(set(e.event_send_port_names), set(['ESP1']))
self.assertEqual(
set(e.alias_names),
set([
'C1__a', 'C2__a', 'C3__a', 'D1__b', 'D2__b', 'D3__b',
'cIn1__a', 'cIn2__a', 'dIn1__b', 'dIn2__b'
]))
self.assertEqual(e.alias('C1__a').rhs, sympy.sympify('cp1__a'))
self.assertIsInstance(e.alias('cIn1__a'), _ReceivePortExposureAlias)
self.assertIsInstance(e.alias('dIn1__b'),
_LocalAnalogReceivePortConnection)
self.assertEqual(set(e.state_variable_names), set(['SV1__a',
'SV1__b']))
self.assertEqual(
e.state_variable('SV1__a').dimension, un.dimensionless)
# - Regimes and Transitions:
self.assertEqual(set(e.regime_names),
set(['r1___r1', 'r1___r2', 'r2___r1', 'r2___r2']))
# =====================================================================
# Regime a=1, b=2
# =====================================================================
r11 = e.regime('r1___r1')
self.assertEqual(r11.num_on_conditions, 2)
self.assertEqual(r11.num_on_events, 1)
oe1 = r11.on_event('ERP1')
self.assertEqual(oe1.num_output_events, 1)
out1 = oe1.output_event('ESP1')
self.assertEqual(out1.port, e.event_send_port('ESP1'))
self.assertEqual(oe1.num_state_assignments, 1)
self.assertEqual(oe1.state_assignment('SV1__a').rhs, 10)
self.assertEqual(set(oe1.state_assignment_variables), set(
('SV1__a', )))
self.assertEqual(r11.num_on_conditions, 2)
oc1 = r11.on_condition('SV1__a > cp1__a')
self.assertEqual(oc1.num_output_events, 1)
self.assertEqual(oc1.target_regime, r11)
out1 = oc1.output_event('ESP1')
self.assertEqual(out1.port, e.event_send_port('ESP1'))
self.assertEqual(oc1.num_state_assignments, 0)
oc2 = r11.on_condition('SV1__b > dp1__b')
self.assertEqual(oc2.num_output_events, 0)
self.assertEqual(oc2.num_state_assignments, 0)
self.assertEqual(oc2.target_regime, r11)
# =====================================================================
# Regime a=1, b=2
# =====================================================================
r12 = e.regime('r1___r2')
self.assertEqual(r12.num_on_conditions, 2)
oc1 = r12.on_condition('SV1__a > cp1__a')
self.assertEqual(set(oc1.output_event_port_names), set(('ESP1', )))
self.assertEqual(oc1.target_regime, r12)
oc2 = r12.on_condition('SV1__b > 1')
self.assertEqual(oc2.num_output_events, 0)
self.assertEqual(oc2.target_regime, r11)
self.assertEqual(r12.num_on_events, 1)
self.assertEqual(
r12.on_event('ERP1').port.port, c.event_receive_port('spikein'))
# =====================================================================
# Regime a=2, b=1
# =====================================================================
r21 = e.regime('r2___r1')
self.assertEqual(r21.num_on_conditions, 2)
oc1 = r21.on_condition('SV1__a > 1')
self.assertEqual(oc1.num_output_events, 0)
self.assertEqual(oc1.num_state_assignments, 0)
self.assertEqual(oc1.target_regime, r11)
oc2 = r21.on_condition('SV1__b > dp1__b')
self.assertEqual(oc2.num_output_events, 0)
self.assertEqual(oc2.num_state_assignments, 0)
self.assertEqual(oc2.target_regime, r21)
self.assertEqual(r21.num_on_events, 0)
# =====================================================================
# Regime a=2, b=2
# =====================================================================
r22 = e.regime('r2___r2')
self.assertEqual(r21.num_on_conditions, 2)
oc1 = r22.on_condition('SV1__a > 1')
self.assertEqual(oc1.num_output_events, 0)
self.assertEqual(oc1.num_state_assignments, 0)
self.assertEqual(oc1.target_regime, r12)
oc2 = r22.on_condition('SV1__b > 1')
self.assertEqual(oc2.num_output_events, 0)
self.assertEqual(oc2.num_state_assignments, 0)
self.assertEqual(oc2.target_regime, r21)
# - Ports & Parameters:
self.assertEqual(set(e.analog_receive_port_names),
set(['ARP1', 'ARP2']))
self.assertEqual(set(e.parameter_names),
set(['cp1__a', 'cp2__a', 'dp1__b', 'dp2__b']))
self.assertEqual(set(e.state_variable_names), set(['SV1__a',
'SV1__b']))
