def get_component():
component = hierachical_iaf_2coba.get_component()
comp = flattening.flatten(component)
# Remap some ports:
RenameSymbol(comp, 'iaf_vthresh', 'V_th')
RenameSymbol(comp, 'iaf_vreset', 'V_reset')
RenameSymbol(comp, 'iaf_taurefrac', 't_ref')
RenameSymbol(comp, 'iaf_vrest', 'E_L')
RenameSymbol(comp, 'iaf_cm', 'C_m')
RenameSymbol(comp, 'iaf_gl', 'g_L')
RenameSymbol(comp, 'cobaExcit_vrev', 'E_ex')
RenameSymbol(comp, 'cobaInhib_vrev', 'E_in')
RenameSymbol(comp, 'cobaInhib_q', 'q_in')
RenameSymbol(comp, 'cobaExcit_q', 'q_ex')
RenameSymbol(comp, 'cobaExcit_tau', 'tau_syn_ex')
RenameSymbol(comp, 'cobaInhib_tau', 'tau_syn_in')
RenameSymbol(comp, 'iaf_V', 'V_m')
RenameSymbol(comp, 'iaf_tspike', 'tspike')
RenameSymbol(comp, 'cobaInhib_g', 'g_in')
RenameSymbol(comp, 'cobaExcit_g', 'g_ex')
RenameSymbol(comp, 'cobaInhib_spikeinput', 'spike_in')
RenameSymbol(comp, 'cobaExcit_spikeinput', 'spike_ex')
return comp
def test(cls, testable_component, build_dir):
component = testable_component()
print ' -- Testing One and a half trips...'
if not component.is_flat():
component = flattening.flatten(component)
xmlfile1 = build_dir + component.name + '1.xml'
xmlfile2 = build_dir + component.name + '2.xml'
print ' -- Saving Component To XML:', xmlfile1
writers.XMLWriter.write(component, xmlfile1)
print ' -- Loading Component To XML.'
reloaded_comp = readers.XMLReader.read(xmlfile1)
print ' -- Checking Components are identical'
validators.ComponentEqualityChecker.check_equal(component, reloaded_comp)
print ' -- Saving Reloaded Component to XML', xmlfile2
writers.XMLWriter.write(reloaded_comp, xmlfile2)
print ' -- Checking the SHA1 Checksum of the two xml files:'
hash1 = file_sha1_hexdigest(xmlfile1)
hash2 = file_sha1_hexdigest(xmlfile2)
print ' -->', hash1
print ' -->', hash2
if hash1 != hash2:
raise ValueError(
'XML files are different. This may not be an error but please report it to the developers')
def write(cls, component, filename):
if not component.is_flat():
component = flattening.flatten(component)
from Cheetah.Template import Template
data = {'component': component}
f = open(filename, "w")
s = Template(tmpl, data).respond()
f.write(s)
f.close()
def write_and_compile_nmodl(component):
build_dir = os.path.join(BUILD_DIR, component.name.replace('-', '_'))
clear_and_recreate_dir(build_dir)
if not component.is_flat():
component = flatten(component)
ComponentModifier.close_all_reduce_ports(component=component)
print ' -- Writing Component to .mod'
modfilename = os.path.join(build_dir, component.name + '.mod').replace('-', '_')
write_nmodldirect(component=component, mod_filename=modfilename, weight_variables={})
compile_nmodl(build_dir)
return build_dir
def write_and_compile_nmodl(component):
build_dir = os.path.join(BUILD_DIR, component.name.replace('-', '_'))
clear_and_recreate_dir(build_dir)
if not component.is_flat():
component = flatten(component)
ComponentModifier.close_all_reduce_ports(component=component)
print ' -- Writing Component to .mod'
modfilename = os.path.join(build_dir,
component.name + '.mod').replace('-', '_')
write_nmodldirect(component=component,
mod_filename=modfilename,
weight_variables={})
compile_nmodl(build_dir)
return build_dir
def write(self, component, filename, flatten=True):
""" Writes a component out to the .dot format"""
from Cheetah.Template import Template
if not component.is_flat() and flatten:
component = flattening.flatten(component)
regime_node_names = dict((regime, 'regime%d' % i)
for i, regime in enumerate(component.regimes))
context = {'component': component,
'regime_node_names': regime_node_names,
'dot_escape': _dot_escape}
regime_text = Template(_regime_node_tmpl_text, context).respond()
# Remove Extra whitespace - otherwise we end
# up with really long squares in the output
p = re.compile(r'\s+')
regime_text = p.sub(' ', regime_text)
f = open(filename, 'w')
f.write(regime_text)
f.close()