def main():
args = get_args()
core = DatapathSniffer(width=args.width, depth=args.depth, domain_data='data', domain_axi='axi')
ports = core.get_ports()
# to avoid submodules of different verilog files to have the same name.
name = args.name
submodule_posfix = f'_w{args.width}_d{args.depth}'
fragment = Fragment.get(core, None)
output = verilog.convert(fragment, name=name, ports=ports)
output = re.sub('\*\)', '*/',re.sub('\(\*','/*', output))
output = output.replace('__', '_')
modules = re.findall(r'^module (\S*) ?\(.*\);', output, re.MULTILINE)
for m in modules:
pattern = m.replace('\\', '\\\\').replace('$', '\$')
with_posfix = m.replace('\\', '\\\\') + submodule_posfix
output = re.sub('^module ' + pattern, 'module ' + with_posfix, output, 0, re.MULTILINE)
output = re.sub('^ ' + pattern, ' ' + with_posfix, output, 0, re.MULTILINE)
with open(args.file, 'w') as f:
f.write(output)
def test_verilog():
from nmigen.hdl.ir import Fragment
from nmigen.back import verilog
ctr = Counter(width=16)
fragment = Fragment.get(ctr, None)
output = verilog.convert(fragment, name='example', ports=[ctr.o])
with open('./example.v', 'w') as f:
f.write(output)
def CPU_to_verilog(core_config: dict, vfile: str):
cpu = Bellatrix(**core_config)
ports = cpu.port_list()
# generate the verilog file
fragment = Fragment.get(cpu, None)
output = verilog.convert(fragment, name='bellatrix_core', ports=ports)
try:
with open(vfile, 'w') as f:
f.write(output)
except EnvironmentError as error:
print(f"Error: {error}. Check if the output path exists.",
file=sys.stderr)
def main():
assert False, 'CLI not implemented!'
args = get_args()
core = WidthConverter(args.input_w, args.output_w)
ports = [core.input[f] for f in core.input.fields]
ports += [core.output[f] for f in core.output.fields]
fragment = Fragment.get(core, None)
output = verilog.convert(fragment, name=args.name, ports=ports)
with open(args.file, 'w') as f:
output = re.sub('\*\)', '*/', re.sub('\(\*', '/*', output))
output = output.replace('__', '_')
f.write(output)
def main_runner(parser, args, maker, fw=None, ports=(), build_args={}):
if args.action == "simulate":
design, platform = maker(simulating=True)
fragment = Fragment.get(design, platform)
with pysim.Simulator(fragment,
vcd_file=args.vcd_file,
gtkw_file=args.gtkw_file,
traces=ports) as sim:
sim.add_clock(args.sync_period)
sim.run_until(args.sync_period * args.sync_clocks,
run_passive=True)
if args.action == "build":
design, platform = maker(simulating=False)
platform.build(design, do_program=args.program, **build_args)
if args.action == "boneload":
import boneload
boneload.boneload(fw(), args.port, args.ram)
def synth(core, ports):
plat = EmptyPlatform()
frag = Fragment.get(core, plat)
rtlil_text = rtlil.convert(frag, ports=ports)
yosys_cmd = ''
with tempfile.TemporaryDirectory() as temp_dir:
with open(temp_dir + '/top.il', 'w') as f:
f.write(rtlil_text)
for file_name, content in plat.extra_files.items():
with open(temp_dir + '/' + file_name, 'wb') as f:
f.write(content)
yosys_cmd += "read_verilog {}\n".format(file_name)
yosys_cmd += 'read_ilang {}\n'.format('top.il')
yosys_cmd += 'synth_xilinx -top top\n'
with open(temp_dir + '/top.ys', 'w') as f:
f.write(yosys_cmd)
subprocess.check_call([require_tool("yosys"), 'top.ys'], cwd=temp_dir)
def assertFormal(self, spec, mode="bmc", depth=1):
caller, *_ = traceback.extract_stack(limit=2)
spec_root, _ = os.path.splitext(caller.filename)
spec_dir = os.path.dirname(spec_root)
spec_name = "{}_{}".format(
os.path.basename(spec_root).replace("test_", "spec_"),
caller.name.replace("test_", ""))
# The sby -f switch seems not fully functional when sby is
# reading from stdin.
if os.path.exists(os.path.join(spec_dir, spec_name)):
shutil.rmtree(os.path.join(spec_dir, spec_name))
config = textwrap.dedent("""\
[options]
mode {mode}
depth {depth}
wait on
[engines]
smtbmc
[script]
read_ilang top.il
prep
[file top.il]
{rtlil}
""").format(mode=mode,
depth=depth,
rtlil=rtlil.convert(Fragment.get(spec, platform="formal")))
with subprocess.Popen([require_tool("sby"), "-f", "-d", spec_name],
cwd=spec_dir,
universal_newlines=True,
stdin=subprocess.PIPE,
stdout=subprocess.PIPE) as proc:
stdout, stderr = proc.communicate(config)
if proc.returncode != 0:
self.fail("Formal verification failed:\n" + stdout)
def _generate(self):
args = self.args
fragment = Fragment.get(self.design, self.platform)
generate_type = args.generate_type
if generate_type is None and args.generate_file:
if args.generate_file.name.endswith(".v"):
generate_type = "v"
if args.generate_file.name.endswith(".il"):
generate_type = "il"
if generate_type is None:
parser.error("specify file type explicitly with -t")
if generate_type == "il":
output = rtlil.convert(fragment,
name=self.name,
ports=self._get_ports())
if generate_type == "v":
output = verilog.convert(fragment,
name=self.name,
ports=self._get_ports())
if args.generate_file:
args.generate_file.write(output)
else:
print(output)
def test_fragment_get(self):
m = Module()
f = Fragment.get(m, platform=None)
print("Length ",len(fw))
data = char_convert(fw)
#print(data)
load(data)
if args.action == "simulate":
print("Simulate")
if check_firmware(args.p): raise
s = Simulator(fw=args.p,asm_file=args.f)
s.run()
if args.action == "gatesim":
print("Gateware Simulation")
if check_firmware(args.p): raise
design = construct.simCPU(platform, fw=args.p, asm_file=args.f)
fragment = Fragment.get(design, platform)
f = open("test.vcd", "w")
dut = design.b.serial_port
data = []
if args.l is None:
st = "the quick brown fox jumps over the lazy dog"
data = sim_data.str_data(st)
else:
# clean the meta sub
for i in MetaSub.subroutines:
print(i.__class__, i._called)
i._called = False
print(args.l)
io_map = design.b.io_map
load_ware = firmware.available[args.l](io_map)
print(load_ware.code())
def build(self):
frag = Fragment.get(self, self.plat)
print(verilog.convert(frag, name='top', ports=self.plat.active_pins()))
def prepare(self):
" build the fragment to assign pins"
Fragment.get(self, self.plat)