spi_freq = 2e6
clk_per_bit = int(clk_freq // spi_freq)
if len(sys.argv) < 2 or sys.argv[1] == "sim":
m = Module()
m.submodules.loopback = loopback = SpiMaster(clk_per_bit, 8)
m.d.comb += loopback.miso.eq(loopback.mosi)
sim = sim.Simulator(m)
sim.add_clock(1.0 / clk_freq)
sim.add_sync_process(_test_loopback(loopback))
with sim.write_vcd("spi.vcd", "spi.gtkw", traces=loopback.ports()):
sim.run()
# while sim.advance():
# input("ENTER to continue...")
elif sys.argv[1] == "build":
class Board(TinyFPGABXPlatform):
p = "p1"
class SpiTest(Elaboratable):
def __init__(self):
pass
def elaborate(self, platform: Platform) -> Module:
m = Module()
clk_freq = int(platform.default_clk_frequency)
clk_freq = 16e6
spi_freq = 2e6
clk_per_bit = int(clk_freq // spi_freq)
if len(sys.argv) < 2 or sys.argv[1] == "sim":
m = Module()
m.submodules.loopback = loopback = MockUart(clk_per_bit, 8)
m.submodules.fport = fport = Fport(clk_freq, loopback, None)
sim = sim.Simulator(m)
sim.add_clock(1.0 / clk_freq)
sim.add_sync_process(_test_loopback(fport))
with sim.write_vcd("fport.vcd", "fport.gtkw", traces=fport.ports()):
sim.run()
# while sim.advance():
# input("ENTER to continue...")
elif sys.argv[1] == "build":
class Board(TinyFPGABXPlatform):
p = "p1"
class SpiTest(Elaboratable):
def __init__(self):
pass
def elaborate(self, platform: Platform) -> Module:
m = Module()
clk_freq = int(platform.default_clk_frequency)
def run(fragment, process):
sim = nmigen.sim.Simulator(fragment)
sim.add_sync_process(process)
sim.add_clock(1 / 10e6)
with sim.write_vcd(vcd_path(request.node)):
sim.run()
def run(fragment, process):
sim = nmigen.sim.Simulator(fragment)
sim.add_process(process)
with sim.write_vcd(vcd_path(request.node)):
sim.run_until(100e-6)
self.clk_freq = clk_freq
def elaborate(self, platform: Platform) -> Module:
m = Module()
m.submodules.uart = self.uart = Uart(clk_freq=clk_freq, baud=self.baud)
m.d.comb += [
self.uart.rx.signal.eq(self.uart.tx.signal),
]
return m
if __name__ == "__main__":
import sys
clk_freq = 12e6
if len(sys.argv) < 2 or sys.argv[1] == "sim":
m = Module()
m.submodules.loopback = loopback = _LoopbackTest(int(clk_freq), 115200)
sim = sim.Simulator(m)
sim.add_clock(1.0 / clk_freq)
sim.add_sync_process(_test_loopback(loopback))
with sim.write_vcd(
"uart.vcd",
"uart.gtkw",
traces=[loopback.uart.tx.signal, loopback.uart.rx.signal]):
sim.run()
if __name__ == "__main__":
import sys
from nmigen_boards.tinyfpga_bx import TinyFPGABXPlatform
clk_freq = 16e6
if len(sys.argv) < 2 or sys.argv[1] == "sim":
m = Module()
m.submodules.loopback = loopback = DShot(int(clk_freq), 600000, 4)
sim = sim.Simulator(m)
sim.add_clock(1.0 / clk_freq)
sim.add_sync_process(_test_loopback(loopback))
with sim.write_vcd("dshot.vcd", "dshot.gtkw", traces=loopback.ports()):
sim.run()
# while sim.advance():
# input("ENTER to continue...")
elif sys.argv[1] == "build":
class Board(TinyFPGABXPlatform):
p = "p1"
class DshotTest(Elaboratable):
def __init__(self):
pass
def elaborate(self, platform: Platform) -> Module:
m = Module()