def process_bus(self):
dut = self.dut
bus = dut.bus
frequency = 1.544e6
period = 1.0 / frequency
tco = 10e-9
data_out = []
for count in range(193 * 28):
yield bus.serclk.i.eq(1)
yield Delay(tco)
yield bus.sync.i.eq(count % 193 == 0)
yield bus.msync.i.eq(count % (193 * 24) == 0)
yield Delay(0.5 * period - tco)
yield bus.serclk.i.eq(0)
yield Delay(0.5 * period)
v = yield bus.ser
data_out.append(v)
while data_out:
s = ''.join([str(v) for v in data_out[:193]])
s_hex = hex(int(s, 2))
print(s_hex)
data_out = data_out[193:]
def process_rx_bus(bus, bits):
frequency = 1.544e6
period = 1.0 / frequency
for count, bit in enumerate(bits):
yield bus.sclk.eq(1)
yield bus.serclk.eq(1)
yield Delay(8e-9)
yield bus.crcsync.eq(count % (193 * 24) == 0)
yield bus.casync.eq(0)
yield Delay(2e-9)
yield bus.ser.eq(int(bit))
yield Delay(220e-9)
yield bus.sync.i.eq(count % 193 == 0)
yield Delay(0.5 * period - 230e9)
yield bus.sclk.eq(0)
yield bus.serclk.eq(0)
yield Delay(0.5 * period)
def assert_rom_banks(self, bank0, bank1):
yield self.mbc.cart_addr.eq(0x0000)
yield Delay(1e-6)
assert (yield self.mbc.rom_bank) == bank0
yield self.mbc.cart_addr.eq(0x4000)
yield Delay(1e-6)
assert (yield self.mbc.rom_bank) == bank1
def write(self, addr, data):
yield self.mbc.cart_addr.eq(addr | 0x8000)
yield Delay(1e-6)
yield self.mbc.cart_addr[15].eq(addr & 0x8000)
yield Delay(1e-6)
yield self.mbc.cart_wr.eq(1)
yield self.mbc.cart_data.eq(data)
yield Delay(1e-6)
yield self.mbc.cart_wr.eq(0)
yield Delay(1e-6)
yield self.mbc.cart_addr[15].eq(1)
yield Delay(1e-6)
def process_framer():
frequency = clock_sclk
period = 1.0 / frequency
data = 'THIS_IS_A_TEST_' * 40
data_bits = ''.join(['{:08b}'.format(ord(v)) for v in data])
for bit in data_bits:
yield sclk.eq(1)
yield Delay(SERCLK_SKEW)
yield serclk.eq(1)
yield Delay(SER_SKEW)
yield ser.eq(int(bit))
yield Delay(period * 0.5 - SERCLK_SKEW - SER_SKEW)
yield sclk.eq(0)
yield Delay(SERCLK_SKEW)
yield serclk.eq(0)
yield Delay(period * 0.5 - SERCLK_SKEW)
def process():
for n, (inputs, expected) in enumerate(DATA):
shift_en, in_value = inputs
yield self.dut.shift_en.eq(shift_en)
yield self.dut.in_value.eq(in_value)
yield Delay(0.25)
if expected is not None:
self.assertEqual((yield self.dut.result), expected, f"case={n}")
yield
def check_process():
yield Delay(1e-6)
for k, expected_value in expected.items():
value = yield getattr(decoder, k)
if isinstance(expected_value, enum.Enum):
value = expected_value.__class__(value)
else:
value = hex(value)
expected_value = hex(expected_value)
with self.subTest(f"decoder.{k}"):
self.assertEqual(value, expected_value)
def process():
for n, (inputs, expected) in enumerate(DATA):
start, r_data, r_rdy = inputs
yield self.dut.start.eq(start)
yield self.dut.r_data.eq(r_data)
yield self.dut.r_rdy.eq(r_rdy)
yield Delay(0.25)
r_en, done, output = expected
self.assertEqual((yield self.dut.r_en), r_en, f"case={n}")
self.assertEqual((yield self.dut.done), done, f"case={n}")
if done:
self.assertEqual((yield self.dut.output), output,
f"case={n}")
yield
def process_test(): yield Delay(100e-9) yield sync.enable.eq(1) yield dut.enable.eq(1) yield dut.data[0].eq(0xaa) yield dut.data[1].eq(0x55) yield dut.data[2].eq(0xff) yield dut.data[3].eq(0x00) for _ in range(2500): slot_t1 = yield sync.slot_t1 yield yield dut.data[0].eq(frame_data_0[slot_t1]) yield dut.data[1].eq(frame_data_1[slot_t1]) yield dut.data[2].eq(frame_data_2[slot_t1]) yield dut.data[3].eq(frame_data_3[slot_t1])
def process():
yield mem.n_oe.eq(0)
yield mem.n_wr.eq(1)
yield mem.data_in.eq(0xFFFFFFFF)
yield Delay(1e-6)
yield mem.addr.eq(1)
yield mem.n_oe.eq(0)
yield Delay(1e-6)
yield mem.n_oe.eq(1)
yield Delay(1e-6)
yield mem.data_in.eq(0xAAAA1111)
yield Delay(1e-6)
yield mem.n_wr.eq(0)
yield Delay(0.2e-6)
yield mem.n_wr.eq(1)
yield Delay(0.2e-6)
yield mem.data_in.eq(0xFFFFFFFF)
yield mem.n_oe.eq(0)
yield Delay(1e-6)
yield mem.addr.eq(0)
yield Delay(1e-6)
def process():
yield latch.n_oe.eq(1)
yield latch.le.eq(1)
yield Delay(1e-6)
yield latch.data_in.eq(0xAAAA1111)
yield Delay(1e-6)
yield latch.data_in.eq(0x1111AAAA)
yield Delay(1e-6)
yield latch.le.eq(0)
yield Delay(1e-6)
yield latch.data_in.eq(0xAAAA1111)
yield Delay(1e-6)
yield latch.le.eq(1)
yield Delay(1e-6)
def process():
for n, (inputs, expected_outputs) in enumerate(DATA):
func, i0, i1, cmd_valid, rsp_ready = inputs
exp_result, exp_rsp_valid, exp_cmd_ready = expected_outputs
yield self.dut.cmd_function_id.eq(func)
yield self.dut.cmd_in0.eq(i0)
yield self.dut.cmd_in1.eq(i1)
yield self.dut.cmd_valid.eq(cmd_valid)
yield self.dut.rsp_ready.eq(rsp_ready)
yield Delay(0.1)
if exp_result is not None:
self.assertEqual((yield self.dut.rsp_out), exp_result)
if exp_rsp_valid is not None:
self.assertEqual((yield self.dut.rsp_valid), exp_rsp_valid)
# We don't currently support returning non-OK responses, so
# if our response is valid, it must be OK.
if exp_rsp_valid:
self.assertTrue((yield self.dut.rsp_ok))
if exp_cmd_ready is not None:
self.assertEqual((yield self.dut.cmd_ready), exp_cmd_ready)
yield
def process():
for n, (inputs, expected_output) in enumerate(DATA):
func, i0, i1 = inputs
yield self.dut.cmd_function_id.eq(func)
yield self.dut.cmd_in0.eq(i0)
yield self.dut.cmd_in1.eq(i1)
yield self.dut.cmd_valid.eq(1)
yield self.dut.rsp_ready.eq(0)
yield
yield self.dut.cmd_valid.eq(0)
yield self.dut.rsp_ready.eq(1)
yield Delay(0.1)
assert (yield from self.wait_response_valid()), (
"op{func}({i0:08X}, {i1:08X}) failed to complete")
actual_output = (yield self.dut.rsp_out)
assert actual_output == expected_output, (
f"\nHEX: op{func}(0x{i0:08X}, 0x{i1:08X}) expected: {expected_output:08X} got: {actual_output:08X}"
+
f"\nDEC: op{func}(0x{i0}, 0x{i1}) expected: {expected_output} got: {actual_output}"
)
yield
def process():
for n, (inputs, outputs) in enumerate(data):
restart, input_depth, w_data, w_en, r_next, r_finished = inputs
yield self.dut.restart.eq(restart)
if input_depth is not None:
yield self.dut.input_depth.eq(input_depth)
yield self.dut.w_data.eq(w_data)
yield self.dut.w_en.eq(w_en)
yield self.dut.r_next.eq(r_next)
yield self.dut.r_finished.eq(r_finished)
yield Delay(0.25)
w_ready, r_ready, r_data = outputs
if w_ready is not None:
self.assertEqual((yield self.dut.w_ready), w_ready,
f"cycle={n}")
if r_ready is not None:
self.assertEqual((yield self.dut.r_ready), r_ready,
f"cycle={n}")
if r_data is not None:
self.assertEqual((yield self.dut.r_data), r_data,
f"cycle={n}")
yield
def process_test(): yield Delay(100e-9) for _ in range(4700): yield
def reset(self):
yield self.mbc.cart_rst.eq(1)
yield Delay(1e-6)
yield self.mbc.cart_rst.eq(0)
yield Delay(1e-6)