def sim(cls):
"""A quick simulation of the transparent latch."""
m = Module()
m.submodules.latch = latch = TransparentLatch(32)
sim = Simulator(m)
def process():
yield latch.n_oe.eq(1)
yield latch.le.eq(1)
yield Delay(1e-6)
yield latch.data_in.eq(0xAAAA1111)
yield Delay(1e-6)
yield latch.data_in.eq(0x1111AAAA)
yield Delay(1e-6)
yield latch.le.eq(0)
yield Delay(1e-6)
yield latch.data_in.eq(0xAAAA1111)
yield Delay(1e-6)
yield latch.le.eq(1)
yield Delay(1e-6)
sim.add_process(process)
with sim.write_vcd("latch.vcd"):
sim.run_until(10e-6)
def sim(cls):
"""A quick simulation of the async memory."""
m = Module()
m.submodules.mem = mem = AsyncMemory(width=32, addr_lines=5)
sim = Simulator(m)
def process():
yield mem.n_oe.eq(0)
yield mem.n_wr.eq(1)
yield mem.data_in.eq(0xFFFFFFFF)
yield Delay(1e-6)
yield mem.addr.eq(1)
yield mem.n_oe.eq(0)
yield Delay(1e-6)
yield mem.n_oe.eq(1)
yield Delay(1e-6)
yield mem.data_in.eq(0xAAAA1111)
yield Delay(1e-6)
yield mem.n_wr.eq(0)
yield Delay(0.2e-6)
yield mem.n_wr.eq(1)
yield Delay(0.2e-6)
yield mem.data_in.eq(0xFFFFFFFF)
yield mem.n_oe.eq(0)
yield Delay(1e-6)
yield mem.addr.eq(0)
yield Delay(1e-6)
sim.add_process(process)
with sim.write_vcd("async_memory.vcd"):
sim.run_until(10e-6)
from nmigen import *
from nmigen.sim import Simulator, Delay, Settle, Passive
from st7789 import *
if __name__ == "__main__":
m = Module()
m.submodules.st7789 = st7789 = ST7789(1)
sim = Simulator(m)
sim.add_clock(4e-8)
def process():
yield st7789.color.eq(0xf800)
yield Passive()
sim.add_process(process)
with sim.write_vcd("test.vcd", "test.gtkw", traces=st7789.ports()):
sim.run_until(30e-6, run_passive=True)
m.next = "FETCH"
with m.Case(3):
with m.If(bus.done):
m.d.sync += [
self.pc.eq(self.wx),
bus.addr.eq(self.sp),
bus.data_in.eq(self.pc[:8]),
bus.en.eq(1),
cycle.eq(4)
]
with m.Case(4):
with m.If(bus.done):
m.next = "FETCH"
with m.Default(): # NOP
m.d.comb += op.eq(OpBlock.NOP)
m.next = "FETCH"
with m.State("HALT"):
pass
return m
if __name__ == "__main__":
import sys, os
from nmigen.sim import Simulator
sys.setrecursionlimit(8192)
sim = Simulator(I8080())
sim.add_clock(1e-4)
with sim.write_vcd("trace.vcd"):
sim.run_until(1, run_passive=True)
self.CPU.data_port.r_data.eq(register_file_r.data),
register_file_w.addr.eq(self.CPU.data_port.addr),
register_file_w.data.eq(self.CPU.data_port.w_data),
register_file_w.en.eq(self.CPU.data_port.w_en)
]
return m
if __name__ == "__main__":
with open("infinite_helloworld.bf", "r") as f:
m = Module()
m.submodules.DUT = DUT = Sim_top(f, brainfuck_array_size=64)
sim = Simulator(m)
def process():
yield DUT.si_data.eq(ord("A"))
yield DUT.si_valid.eq(0)
yield DUT.so_ready.eq(0)
for _ in range(3210):
yield
yield DUT.si_valid.eq(1)
yield DUT.so_ready.eq(1)
yield
sim.add_clock(0.02083e-6, domain="sync")
sim.add_sync_process(process)
with sim.write_vcd("bf_tb.vcd", "bf_tb.gtkw"):
sim.run_until(500e-5, run_passive=True)