def process(self) -> test_util.CoroutineProcess[None]:
yield Passive()
while True:
events = yield from test_util.WaitSync(self.decoder.events)
yield
if not (events & (1 << spi.BusEvent.START)):
continue
dc = None
bits = []
while True:
events = yield from test_util.WaitSync(self.decoder.events)
if events & (1 << spi.BusEvent.SAMPLE):
bit = yield self.pins.mosi
bits.append(bit)
if len(bits) == 8:
dc = yield self.pins.dc
self.tc.assertIsNotNone(dc)
self.tc.assertEqual(len(bits), 8)
if dc:
yield from self.emit(DataEvent(ByteFromBits(bits)))
else:
yield from self.emit(
CommandEvent(ByteFromBits(bits)))
dc = None
bits = []
if events & (1 << spi.BusEvent.STOP):
self.tc.assertEqual(bits, [])
yield
yield
def SlaveDoOne(slave: spi.ShiftSlave, miso_data: int, size: int):
"""Simulation only: await and complete a transaction."""
yield slave.register.word_in.eq(miso_data << slave.register.width - size)
yield slave.register.latch.eq(1)
yield # Start
yield slave.register.latch.eq(0)
yield from test_util.WaitSync(slave.start)
yield from test_util.WaitSync(slave.done)
def sequencer_process():
yield sequencer.enable.eq(1)
yield
yield from test_util.WaitSync(
sequencer.status == pmod_oled.PowerStatus.READY)
yield sequencer.enable.eq(0)
yield
yield from test_util.WaitSync(
sequencer.status == pmod_oled.PowerStatus.OFF)
def receive():
yield Passive()
for _ in range(runs):
data = bytearray()
for _ in range(len(expected)):
yield from test_util.WaitSync(rx.start)
yield from test_util.WaitSync(rx.done)
data.append((yield rx.data))
self.assertEqual(data, expected)
yield rx_done.eq(rx_done + 1)
def transmit():
yield Passive()
for i in range(runs):
yield from test_util.WaitSync(rx_done >= i)
yield tx.data.eq(ord(c))
yield tx.start.eq(1)
yield
yield tx.start.eq(0)
yield from test_util.WaitSync(tx.done)
yield tx_done.eq(tx_done + 1)
def MasterDoOne(master: spi.ShiftMaster.Interface, mosi_data: int, size: int):
"""Simulation only: initiate and complete a transaction."""
yield from master.WriteMosi(C(mosi_data, size))
yield master.start.eq(1)
yield # Start
yield master.start.eq(0)
yield from test_util.WaitSync(master.done)
miso_data = yield master.ReadMiso(size)
return miso_data
def convert():
yield b2d.input.eq(input)
yield b2d.start.eq(1)
yield # Update input and start
yield from test_util.WaitSync(b2d.done)
actual = yield from test_util.YieldList(b2d.output)
print(f'Input: {input}')
print(f'Expected: {expected}')
print(f'Actual: {actual}')
self.assertEqual(expected, actual)
def clock_monitor():
yield Passive()
last_edge = None
while True:
yield from test_util.WaitSync(clk_edge.rose)
now = yield timestamp
if last_edge is not None:
self.assertEqual(now - last_edge, 10)
last_edge = now
yield
def process():
yield Passive()
example = EXAMPLES[n]
yield from test_util.WaitSync(mux.select == n)
actual = yield from MasterDoOne(mux.interfaces[n],
example.mosi_data,
example.size)
self.assertEqual(actual, example.miso_data)
yield master_finish[n].eq(1)
yield mux.select.eq(mux.select + 1)
def convert():
for sig, val in zip(bcdr.input, input):
yield sig.eq(val)
yield bcdr.start.eq(1)
yield # Update input and start
yield from test_util.WaitSync(bcdr.done)
actual = yield from test_util.YieldList(bcdr.output)
print(f'Input: {input}')
print(f'Expected: {expected}')
print(f'Actual: {actual}')
self.assertEqual(expected, actual)
def convert_one(rval: int, expected_rdisp: List[int],
expected_ldisp: List[int]):
yield conv.rval.eq(rval)
yield conv.lval.eq(2 * rval)
yield # Let conv automatically detect the update
yield from test_util.WaitSync(conv.done)
actual_rdisp = yield from test_util.YieldList(conv.rdisp)
actual_ldisp = yield from test_util.YieldList(conv.ldisp)
print(f'Input: {rval}')
print(f'Expected: {expected_rdisp}, {expected_ldisp}')
print(f'Actual: {actual_rdisp}, {actual_ldisp}')
self.assertEqual(expected_rdisp, actual_rdisp)
self.assertEqual(expected_ldisp, actual_ldisp)
def wait_done():
yield from test_util.WaitSync((tx_done == runs)
& (rx_done == runs))
def wait_finish():
yield from test_util.WaitSync(finish)
