def per_job(job):
def get_substs(mode="IREG_OREG", program=[]):
if mode == "NONE":
comment = "//"
program = ""
else:
comment = ""
program = "program " + "\n\t\t\t".join(
['"' + _ + ' "' for _ in program])
return dict(loc=loc, mode=mode, program=program, comment=comment)
cfg = job["cfg"]
loc = job["site"]
iol = job["iol"]
cfg.setup()
empty_bitfile = cfg.build_design(cfg.ncl, {})
cfg.ncl = "iologic.ncl"
modes = [
"NONE", "IREG_OREG", "IDDRX1_ODDRX1", "IDDRXN", "ODDRXN",
"MIDDRX_MODDRX"
]
tie_program = ["LSRIMUX:0", "LSROMUX:0"]
nonrouting.fuzz_enum_setting(
cfg, "IOLOGIC{}.MODE".format(iol), modes,
lambda x: get_substs(mode=x, program=["MODE:" + x] + tie_program),
empty_bitfile, False)
def per_site(s):
site, prim = s
def get_substs(mode="NONE", default_cfg=False, kv=None, mux=False, extra_sigs=""):
if kv is None:
config = ""
elif mux:
val = "#SIG"
if kv[1] in ("0", "1"):
val = kv[1]
if kv[1] == "INV":
val = "#INV"
config = "{}::::{}={}{}".format(mode, kv[0], val, extra_sigs)
else:
config = "{}:::{}={}".format(mode, kv[0], kv[1])
return dict(mode=mode, cmt="//" if mode == "NONE" else "", config=config, prim=prim, site=site)
nonrouting.fuzz_enum_setting(cfg, empty, "{}.MODE".format(prim), ["NONE", prim],
lambda x: get_substs(mode=x), False,
desc="{} primitive mode".format(prim))
for name, values, desc in settings[prim]:
nonrouting.fuzz_enum_setting(cfg, empty, "{}.{}".format(prim, name), values,
lambda x: get_substs(mode=prim, kv=(name, x)), False,
desc=desc)
if prim in words:
for name, width, desc in words[prim]:
nonrouting.fuzz_word_setting(cfg, "{}.{}".format(prim, name), width,
lambda x: get_substs(mode=prim, kv=(name, "0b" + "".join(reversed(["1" if b else "0" for b in x])))),
desc=desc)
def per_job(job):
def get_substs(settings, cibout="OFF", outclk="CLK0"):
route = ""
if cibout == "ON":
if mult == "DSP_RIGHT" or mult == "MULT18_4":
route = "route\n\t\t\t" + rc + "_JP0_MULT18." + rc + "_JF4;"
elif mult == "MULT18_1":
route = "route\n\t\t\t" + rc + "_JP0_MULT18.R13C4_JQ0;"
elif mult == "MULT18_5":
route = "route\n\t\t\t" + rc + "_JP0_MULT18.R13C8_JQ4;"
else:
route = "route\n\t\t\t" + rc + "_JP0_MULT18." + rc + "_JF0;"
return dict(loc=loc, route=route, rc=rc, outclk=outclk)
loc, mult, cfg = job
rc = loc.split("_")[1]
cfg.setup()
empty_bitfile = cfg.build_design(cfg.ncl, {})
cfg.ncl = "dspconfig.ncl"
if mult.startswith("MULT"):
nonrouting.fuzz_enum_setting(
cfg, "{}.CIBOUT_BYP".format(mult), ["OFF", "ON"],
lambda x: get_substs(settings={},
cibout="ON",
outclk=("NONE" if x == "ON" else "CLK0")),
empty_bitfile, False)
else:
nonrouting.fuzz_enum_setting(
cfg, "{}.CIBOUT".format(mult), ["OFF", "ON"],
lambda x: get_substs(settings={}, cibout=x), empty_bitfile,
False)
def per_job(job):
def get_substs(mode="CLKDIVF", div="2.0", gsr="ENABLED"):
if mode == "NONE":
comment = "//"
else:
comment = ""
return dict(site=loc, comment=comment, div=div, gsr=gsr)
cfg, loc, rc = job
cfg.setup()
empty_bitfile = cfg.build_design(cfg.ncl, {})
cfg.ncl = "clkdiv.ncl"
nonrouting.fuzz_enum_setting(cfg, "{}.DIV".format(loc), ["2.0", "3.5"],
lambda x: get_substs(div=x),
empty_bitfile)
nonrouting.fuzz_enum_setting(cfg, "{}.GSR".format(loc),
["ENABLED", "DISABLED"],
lambda x: get_substs(gsr=x),
empty_bitfile)
idx = loc[-1]
nets = [
"{}_JCDIVX_CLKDIV{}".format(rc, idx),
"{}_CLKI_CLKDIV{}".format(rc, idx),
"{}_JRST_CLKDIV{}".format(rc, idx),
"{}_JALIGNWD_CLKDIV{}".format(rc, idx),
"{}_CLKI{}".format(rc, idx),
]
cfg.ncl = "clkdiv_routing.ncl"
interconnect.fuzz_interconnect_with_netnames(cfg, nets, bidir=True)
def per_pin(pin):
def get_substs(sig, val):
if val == pin:
val = "#SIG"
subs = {"sig": sig, "val": val}
return subs
if pin.startswith("JCE"):
options = [pin, "1"]
elif pin.startswith("JCLK") or pin.startswith("JLSR"):
options = [pin, "0"]
else:
options = [pin, "0", "1"]
# Load the EBR database and find the correct signal
ebrdb = pytrellis.get_tile_bitdata(
pytrellis.TileLocator(cfg.family, cfg.device, "MIB_EBR4"))
fconns = ebrdb.get_fixed_conns()
sig = None
for conn in fconns:
if conn.source.endswith(pin):
sig = conn.sink
break
assert sig is not None
# Convert net name to NCL pin name by stripping extraneous content
if sig[0] == "J":
sig = sig[1:]
sig = sig.replace("_EBR", "")
nonrouting.fuzz_enum_setting(cfg, "CIB.{}MUX".format(pin), options,
lambda x: get_substs(sig=sig, val=x),
empty_bitfile, False)
def per_slice(slicen):
def get_substs(ij1_0="YES", ij1_1="YES"):
return dict(slice=slicen, ij1_0=ij1_0, ij1_1=ij1_1)
nonrouting.fuzz_enum_setting(cfg, "SLICE{}.CCU2.INJECT1_0".format(slicen), ["YES", "NO"],
lambda x: get_substs(ij1_0=x),
empty_bitfile, True)
nonrouting.fuzz_enum_setting(cfg, "SLICE{}.CCU2.INJECT1_1".format(slicen), ["YES", "NO"],
lambda x: get_substs(ij1_1=x),
empty_bitfile, True)
def per_clk(clkn):
def get_substs(clkmux):
if clkmux == "INV":
clkmux = "CLK:::CLK=#INV"
return dict(c=clkn, clkmux=clkmux)
nonrouting.fuzz_enum_setting(cfg, "CLK{}.CLKMUX".format(clkn),
["CLK", "INV"],
lambda x: get_substs(clkmux=x),
empty_bitfile, True)
def per_slice(slicen):
def get_substs(wremux):
if wremux == "INV":
wremux = "WRE:::WRE=#INV"
if wremux == "0":
wremux = "1:::1=0"
return dict(slice=slicen, wremux=wremux)
nonrouting.fuzz_enum_setting(cfg, "SLICE{}.WREMUX".format(slicen), ["0", "1", "WRE", "INV"],
lambda x: get_substs(wremux=x),
empty_bitfile, False)
def per_lsr(lsrn):
def get_substs(lsrmux="LSR", srmode="LSR_OVER_CE"):
if lsrmux == "INV":
lsrmux = "LSR:::LSR=#INV"
return dict(l=lsrn, lsrmux=lsrmux, srmode=srmode)
nonrouting.fuzz_enum_setting(cfg, "LSR{}.LSRMUX".format(lsrn), ["LSR", "INV"],
lambda x: get_substs(lsrmux=x),
empty_bitfile, True)
nonrouting.fuzz_enum_setting(cfg, "LSR{}.SRMODE".format(lsrn), ["LSR_OVER_CE", "ASYNC"],
lambda x: get_substs(srmode=x),
empty_bitfile, True)
def main():
cfg.setup()
empty = cfg.build_design(cfg.sv, {})
cfg.sv = "speed_40.v"
nonrouting.fuzz_enum_setting(
cfg,
empty,
"CHIP.SPEED", ["SLOW_1V0", "FAST_1V0"],
lambda x: {"speed": speed_map[x]},
True,
desc="Adjust back bias for high speed or low power")
def main():
pytrellis.load_database("../../../database")
cfg.setup()
empty_bitfile = cfg.build_design(cfg.ncl, {})
cfg.ncl = "cclk.ncl"
nonrouting.fuzz_enum_setting(cfg, "CCLK.MODE", ["NONE", "USRMCLK"],
lambda x: get_substs(mode=x), empty_bitfile)
cfg.ncl = "cclk_routing.ncl"
interconnect.fuzz_interconnect_with_netnames(
cfg, ["R71C0_JPADDT_CCLK", "R71C0_JPADDO_CCLK", "R71C0_JPADDI_CCLK"],
bidir=True)
def per_slice(slicen):
def get_substs(cemux):
if cemux == "INV":
cemux = "CE:::CE=#INV"
if cemux == "0":
cemux = "1:::1=0"
return dict(slice=slicen, cemux=cemux)
nonrouting.fuzz_enum_setting(cfg, "SLICE{}.CEMUX".format(slicen),
["0", "1", "CE", "INV"],
lambda x: get_substs(cemux=x),
empty_bitfile, False)
def per_slice(slicen):
def get_substs(sig="A0", conn="A0"):
subs = {"slice": slicen}
if conn == "1":
subs["muxcfg"] = "::{}=1".format(sig)
else:
subs["muxcfg"] = ""
return subs
for sig in ["A0", "A1", "B0", "B1", "C0", "C1", "D0", "D1"]:
nonrouting.fuzz_enum_setting(cfg, "SLICE{}.{}MUX".format(slicen, sig), [sig, "1"],
lambda x: get_substs(sig=sig, conn=x),
empty_bitfile, False)
def per_slice(slicen):
def get_substs(m0mux="M0", m1mux="M1"):
return dict(slice=slicen, m0mux=m0mux, m1mux=m1mux)
nonrouting.fuzz_enum_setting(cfg, "SLICE{}.M0MUX".format(slicen),
["M0", "1"],
lambda x: get_substs(m0mux=x),
empty_bitfile, False)
nonrouting.fuzz_enum_setting(cfg, "SLICE{}.M1MUX".format(slicen),
["M1", "1"],
lambda x: get_substs(m1mux=x),
empty_bitfile, False)
def per_job(job):
def get_substs(mode="", settings={}, program={}, route=""):
if mode == "" or mode == "NONE":
delay = ""
else:
delay = ",".join(
["DELAY:::DEL_MODE={}".format(mode)] +
["{}={}".format(k, v) for k, v in settings.items()])
program = " ".join(
["{}:{}".format(k, v) for k, v in program.items()])
if side in ("T, B"):
s = "S"
else:
s = ""
if route != "":
route = "route\n\t\t{}_IOLDO{}.{}_IOLDO{}_PIO,\n\t\t{}_IOLDOD{}_{}IOLOGIC.{}_IOLDO{};".format(
rc, iol, rc, iol, rc, iol, s, rc, iol)
return dict(loc=loc,
delay=delay,
program=program,
route=route,
s=s)
cfg = job["cfg"]
loc = job["site"]
iol = job["iol"]
side = job["side"]
rc = job["rc"]
cfg.setup()
empty_bitfile = cfg.build_design(cfg.ncl, {})
cfg.ncl = "iologic.ncl"
nonrouting.fuzz_enum_setting(
cfg, "IOLOGIC{}.DELAY.OUTDEL".format(iol), ["DISABLED", "ENABLED"],
lambda x: get_substs(route=(x if x != "DISABLED" else "")),
empty_bitfile, False)
nonrouting.fuzz_enum_setting(
cfg, "IOLOGIC{}.DELAY.WAIT_FOR_EDGE".format(iol),
["DISABLED", "ENABLED"],
lambda x: get_substs(mode="USER_DEFINED",
settings={
"DEL_VALUE": 0,
"WAIT_FOR_EDGE": x
}), empty_bitfile, False)
nonrouting.fuzz_word_setting(
cfg, "IOLOGIC{}.DELAY.DEL_VALUE".format(iol), 7,
lambda x: get_substs(mode="USER_DEFINED",
settings={
"DEL_VALUE": todecstr(x),
"WAIT_FOR_EDGE": "DISABLED"
}), empty_bitfile)
def per_slice(slicen):
def get_substs(mode):
return dict(slice=slicen, mode=mode)
if slicen == "A" or slicen == "B":
modes = ["LOGIC", "CCU2", "DPRAM"]
elif slicen == "C":
modes = ["LOGIC", "CCU2", "RAMW"]
else:
modes = ["LOGIC", "CCU2"]
nonrouting.fuzz_enum_setting(cfg, "SLICE{}.MODE".format(slicen), modes,
lambda x: get_substs(mode=x),
empty_bitfile, False)
def main():
pytrellis.load_database("../../../database")
cfg.setup()
empty_bitfile = cfg.build_design(cfg.ncl, {})
cfg.ncl = "dtr.ncl"
nonrouting.fuzz_enum_setting(cfg, "DTR.MODE", ["NONE", "DTR"],
lambda x: get_substs(mode=x), empty_bitfile)
cfg.ncl = "dtr_routing.ncl"
interconnect.fuzz_interconnect_with_netnames(
cfg, ["R70C22_JSTARTPULSE_DTR"] +
["R70C22_JDTROUT{}_DTR".format(i) for i in range(8)],
bidir=True)
def per_clk(clkn):
slices = {"0": "A", "1": "B", "2": "C", "3": "D"}
def get_substs(clkmux):
if clkmux == "INV":
clkmux = "CLK:::CLK=#INV"
if clkmux == "1":
clkmux = "0:::0=1"
return dict(c=slices[clkn], clkmux=clkmux)
nonrouting.fuzz_enum_setting(cfg, "CLK{}.CLKMUX".format(clkn),
["CLK", "INV", "0", "1"],
lambda x: get_substs(clkmux=x),
empty_bitfile, True)
def main():
pytrellis.load_database("../../../database")
cfg.setup()
empty_bitfile = cfg.build_design(cfg.ncl, {})
cfg.ncl = "osc.ncl"
nonrouting.fuzz_enum_setting(cfg, "OSC.MODE", ["NONE", "OSCG"],
lambda x: get_substs(mode=x), empty_bitfile)
nonrouting.fuzz_enum_setting(cfg, "OSC.DIV",
["{}".format(i) for i in range(2, 128)],
lambda x: get_substs(div=x), empty_bitfile)
cfg.ncl = "osc_routing.ncl"
interconnect.fuzz_interconnect_with_netnames(cfg, ["R70C4_JOSC_OSC"],
bidir=True)
def per_job(job):
def get_substs(mode="ECLKSYNCB"):
if mode == "NONE":
comment = "//"
else:
comment = ""
return dict(site=loc, comment=comment)
cfg, loc = job
cfg.setup()
empty_bitfile = cfg.build_design(cfg.ncl, {})
cfg.ncl = "eclksync.ncl"
nonrouting.fuzz_enum_setting(cfg, "{}.MODE".format(loc), ["NONE", "ECLKSYNCB"],
lambda x: get_substs(mode=x), empty_bitfile, False)
def per_cib(cib):
rc, cfg = cib
cfg.setup()
empty = cfg.build_design(cfg.sv, {})
r, c = rc
# CIB F/Q "used" bits
nodes = ["R{}C{}_JF{}".format(r, c, i) for i in range(8)]
nodes += ["R{}C{}_JQ{}".format(r, c, i) for i in range(8)]
node_data = lapie.get_node_data(cfg.udb, nodes)
for n in node_data:
to_wire = n.name
setting_name = to_wire.split("_")[1] + "_USED"
from_wire = None
for p in n.uphill_pips:
if "CIBTEST" not in p.from_wire:
from_wire = p.from_wire
break
assert from_wire is not None
arcs_attr = r', \dm:arcs ="{}.{}"'.format(to_wire, from_wire)
nonrouting.fuzz_enum_setting(
cfg, empty, "CIB." + setting_name, ["NO", "YES"],
lambda x: dict(arcs_attr=arcs_attr)
if x == "YES" else {}, False)
# CIBMUXIN -> CIBMUXOUT
cfg.sv = "cib_iomux_40.v"
for x in ("A", "B", "C", "D"):
# Stop Radiant trying to tie unused outputs; as this causes weird bit patterns
extra_arcs = []
for i in range(8):
for x2 in ("A", "B", "C", "D"):
if x2 == x:
continue
extra_arcs.append(
"R{r}C{c}_JCIBMUXOUT{x}{i}.R{r}C{c}_JCIBMUXINA{i}".
format(r=r, c=c, x=x2, i=i))
cibmuxout = [
"R{}C{}_JCIBMUXOUT{}{}".format(r, c, x, i) for i in range(8)
]
fuzz_interconnect(
config=cfg,
nodenames=cibmuxout,
regex=False,
bidir=False,
full_mux_style=True,
extra_substs=dict(extra_arc=" ".join(extra_arcs)))
def main():
pytrellis.load_database("../../database")
for job in jobs:
cfg = job["cfg"]
side = job["side"]
pin = job["pin"]
cfg.setup()
empty_bitfile = cfg.build_design(cfg.ncl, {})
cfg.ncl = "pio.v"
def get_substs(iomode, extracfg=None):
if iomode == "NONE":
iodir, type = "NONE", ""
else:
iodir, type = iomode.split("_", 1)
substs = {
"dir": iodir,
"io_type": type,
"loc": pin,
"extra_attrs": ""
}
if extracfg is not None:
substs["extra_attrs"] = '(* {}="{}" *)'.format(
extracfg[0], extracfg[1])
return substs
vcco_opts = {
"1V2": "OUTPUT_LVCMOS12",
"1V5": "OUTPUT_LVCMOS15",
"1V8": "OUTPUT_LVCMOS18",
"2V5": "OUTPUT_LVCMOS25",
"3V3": "OUTPUT_LVCMOS33",
"NONE": "INPUT_LVCMOS12",
}
nonrouting.fuzz_enum_setting(cfg, "BANK.VCCIO",
list(sorted(vcco_opts.keys())),
lambda x: get_substs(iomode=vcco_opts[x]),
empty_bitfile)
if side in ('L', 'R'):
nonrouting.fuzz_enum_setting(
cfg, "BANK.DIFF_REF", ["OFF", "ON"],
lambda x: get_substs(iomode="INPUT_LVCMOS33D"
if x == "ON" else "INPUT_LVCMOS33"),
empty_bitfile)
nonrouting.fuzz_enum_setting(
cfg, "BANK.LVDSO", ["OFF", "ON"],
lambda x: get_substs(iomode="OUTPUT_LVDS"
if x == "ON" else "OUTPUT_LVCMOS25D"),
empty_bitfile)
nonrouting.fuzz_enum_setting(
cfg, "BANK.VREF", ["OFF", "ON"],
lambda x: get_substs(iomode="INPUT_SSTL15_II"
if x == "ON" else "INPUT_LVDS"),
empty_bitfile)
def per_slice(slicen):
def get_substs(mode="LOGIC", kv=None):
if kv is None:
config = ""
else:
config = "{}:::{}={}".format(mode, kv[0], kv[1])
return dict(z=slicen, mode=mode, config=config)
modes = ["LOGIC", "CCU2"]
if slicen in ("A", "B"):
modes.append("DPRAM")
if slicen == "C":
modes.append("RAMW")
nonrouting.fuzz_enum_setting(cfg, empty, "SLICE{}.MODE".format(slicen),
modes, lambda x: get_substs(x), False)
nonrouting.fuzz_enum_setting(
cfg, empty, "SLICE{}.CCU2.INJECT".format(slicen), ["YES", "NO"],
lambda x: get_substs("CCU2", ("INJECT", x)), False)
def main():
for config in configs:
cfg = config["cfg"]
cfg.setup()
r, c = config["rc"]
nodes = ["R{}C{}_*".format(r, c)]
def nodename_filter(x, nodes):
return ("R{}C{}_".format(r, c) in x) and ("ECLKDDR" in x or "DDRDLL_CORE" in x or "JCLKOUT_I" in x or "JPCLK_I" in x or "JECLK" in x)
def pip_filter(x, nodes):
src, snk = x
return True
fuzz_interconnect(config=cfg, nodenames=nodes, nodename_predicate=nodename_filter, pip_predicate=pip_filter, regex=True, bidir=True, ignore_tiles=ignore_tiles)
cfg.sv = "../shared/empty_40.v"
empty = cfg.build_design(cfg.sv, {})
cfg.sv = "ddrdll.v"
site = "DDRDLL_CORE_R{}C{}".format(r, c)
def get_substs(mode="DDRDLL_CORE", kv=None, mux=False):
if kv is None:
config = ""
elif mux:
val = "#SIG"
if kv[1] in ("0", "1"):
val = kv[1]
if kv[1] == "INV":
val = "#INV"
config = "{}::::{}={}".format(mode, kv[0], val)
else:
config = "{}:::{}={}".format(mode, kv[0], kv[1])
return dict(mode=mode, cmt="//" if mode == "NONE" else "", config=config, site=site)
nonrouting.fuzz_enum_setting(cfg, empty, "DDRDLL.MODE", ["NONE", "DDRDLL_CORE"],
lambda x: get_substs(mode=x), False,
desc="DDRDLL primitive mode")
nonrouting.fuzz_enum_setting(cfg, empty, "DDRDLL.GSR", ["ENABLED", "DISABLED"],
lambda x: get_substs(kv=("GSR", x)), False,
desc="DDRDLL GSR mask")
nonrouting.fuzz_enum_setting(cfg, empty, "DDRDLL.ENA_ROUNDOFF", ["ENABLED", "DISABLED"],
lambda x: get_substs(kv=("ENA_ROUNDOFF", x)), False)
nonrouting.fuzz_enum_setting(cfg, empty, "DDRDLL.FORCE_MAX_DELAY", ["CODE_OR_LOCK_FROM_DLL_LOOP", "FORCE_LOCK_AND_CODE"],
lambda x: get_substs(kv=("FORCE_MAX_DELAY", x)), False)
nonrouting.fuzz_enum_setting(cfg, empty, "DDRDLL.RSTMUX", ["RST", "INV"],
lambda x: get_substs(kv=("RST", x), mux=True), False)
def main():
pytrellis.load_database("../../../database")
cfg.setup()
empty_bitfile = cfg.build_design(cfg.ncl, {})
nonrouting.fuzz_enum_setting(cfg, "SYSCONFIG.DONEPHASE", ["T0", "T1", "T2", "T3"],
lambda x: get_substs(dict(DONEPHASE=x)), empty_bitfile, False)
nonrouting.fuzz_enum_setting(cfg, "SYSCONFIG.GOEPHASE", ["T1", "T2", "T3"],
lambda x: get_substs(dict(GOEPHASE=x)), empty_bitfile, False)
nonrouting.fuzz_enum_setting(cfg, "SYSCONFIG.GSRPHASE", ["T1", "T2", "T3"],
lambda x: get_substs(dict(GSRPHASE=x)), empty_bitfile, False)
nonrouting.fuzz_enum_setting(cfg, "SYSCONFIG.GWEPHASE", ["T1", "T2", "T3"],
lambda x: get_substs(dict(GWEPHASE=x)), empty_bitfile, False)
def per_job(job):
def get_substs(mode="PCSCLKDIV", program=None):
if mode == "NONE":
comment = "//"
else:
comment = ""
if program is not None:
program = ":::" + ",".join(
["{}={}".format(k, v) for k, v in program.items()])
else:
program = ":#ON"
return dict(loc=loc, comment=comment, program=program)
cfg, loc, rc = job
cfg.setup()
empty_bitfile = cfg.build_design(cfg.ncl, {})
cfg.ncl = "pcsclkdiv.ncl"
nonrouting.fuzz_enum_setting(
cfg, "{}.MODE".format(loc), ["NONE", "PCSCLKDIV"],
lambda x: get_substs(mode=x, program={"GSR": "ENABLED"}),
empty_bitfile, False)
nonrouting.fuzz_enum_setting(cfg, "{}.GSR".format(loc),
["DISABLED", "ENABLED"],
lambda x: get_substs(program={"GSR": x}),
empty_bitfile, False)
cfg.ncl = "pcsclkdiv_routing.ncl"
nets = [
"{}_JRST_{}".format(rc, loc),
"{}_JSEL2_{}".format(rc, loc),
"{}_JSEL1_{}".format(rc, loc),
"{}_JSEL0_{}".format(rc, loc),
"{}_CDIV1_{}".format(rc, loc),
"{}_CDIVX_{}".format(rc, loc),
"{}_CLKI_{}".format(rc, loc),
"{}_PCSCDIVI{}".format(rc, loc[-1]),
"{}_JPCSCDIVCIB{}".format(rc, loc[-1]),
]
interconnect.fuzz_interconnect_with_netnames(
cfg,
nets,
bidir=True,
)
def per_job(job):
def get_substs(mode=""):
if mode != "NONE":
mode = "IDDRXN:::DDRMODE={}".format(mode)
else:
mode = ""
return dict(loc=loc, mode=mode)
cfg = job["cfg"]
loc = job["site"]
iol = job["iol"]
side = job["side"]
cfg.setup()
empty_bitfile = cfg.build_design(cfg.ncl, {})
cfg.ncl = "iologic.ncl"
nonrouting.fuzz_enum_setting(cfg, "IOLOGIC{}.IDDRXN.MODE".format(iol), ["NONE", "IDDRX2", "IDDR71"],
lambda x: get_substs(mode=x), empty_bitfile, False)
def per_job(job):
cfg, side, N = job
cfg.setup()
empty_bitfile = cfg.build_design(cfg.ncl, {})
cfg.ncl = "dcc.ncl"
for i in range(N):
def get_substs(mode="DCCA"):
if mode == "NONE":
comment = "//"
else:
comment = ""
return dict(site=loc, comment=comment)
loc = "DCC_{}{}".format(side, i)
nonrouting.fuzz_enum_setting(cfg, "{}.MODE".format(loc),
["NONE", "DCCA"],
lambda x: get_substs(mode=x),
empty_bitfile, False)
def main():
pytrellis.load_database("../../../database")
for job in jobs:
cfg = job["cfg"]
side = job["side"]
pin = job["pin"]
cfg.setup()
empty_bitfile = cfg.build_design(cfg.ncl, {})
cfg.ncl = "pio.v"
def get_substs(iomode, vcc, extracfg=None):
if iomode == "NONE":
iodir, type = "NONE", ""
else:
iodir, type = iomode.split("_", 1)
substs = {
"dir": iodir,
"io_type": type,
"loc": pin,
"extra_attrs": "",
"vcc": vcc
}
if extracfg is not None:
substs["extra_attrs"] = '(* {}="{}" *)'.format(
extracfg[0], extracfg[1])
return substs
vcco_opts = {
"1V2": "OUTPUT_LVCMOS12",
"1V5": "OUTPUT_LVCMOS15",
"1V8": "OUTPUT_LVCMOS18",
"2V5": "OUTPUT_LVCMOS25",
"3V3": "OUTPUT_LVCMOS33",
"NONE": "INPUT_LVCMOS12",
}
nonrouting.fuzz_enum_setting(
cfg, "BANK.VCCIO", list(sorted(vcco_opts.keys())),
lambda x: get_substs(iomode=vcco_opts[x],
vcc=x.replace("V", ".")
if x != "NONE" else "2.5"), empty_bitfile)
def per_job(job):
def get_substs(net, value):
if net == value:
settings = "{}=#SIG".format(net, net)
else:
settings = "{}=#INV".format(net)
return dict(loc=loc, mode=mode, settings=settings,
cmodel=cellmodel)
loc, mult, cfg = job
cellmodel = loc.split("_")[0]
mode = "MULT18X18D" if cellmodel == "MULT18" else "ALU54B"
cfg.setup()
empty_bitfile = cfg.build_design(cfg.ncl, {})
cfg.ncl = "dspconfig.ncl"
for port in ["CLK", "CE", "RST"]:
for i in range(4):
sig = port + str(i)
nonrouting.fuzz_enum_setting(cfg, "{}.{}MUX".format(mult, sig), [sig, "INV"],
lambda x: get_substs(sig, x), empty_bitfile,
False)