def test_find_module_filename_usr_paths(self):
module_name = "wb_test"
loc = os.path.join( os.path.dirname(__file__),
os.path.pardir,
"fake")
result = utils.find_module_filename(module_name, user_paths = [loc], debug = self.dbg)
self.assertEqual(len(result) > 0, True)
def test_find_module_filename_usr_paths(self):
module_name = "wb_test"
loc = os.path.join(os.path.dirname(__file__), os.path.pardir, "fake")
result = utils.find_module_filename(module_name,
user_paths=[loc],
debug=self.dbg)
self.assertEqual(len(result) > 0, True)
def add_box(self, box_type, color, name, ID, position, rect=QRect()):
"""Add a box to the canvas"""
scene = self.canvas.scene()
if box_type == BoxType.SLAVE:
fn = utils.find_module_filename(name, utils.get_local_verilog_paths())
fn = utils.find_rtl_file_location(fn, utils.get_local_verilog_paths())
if self.model is None:
raise DesignControlError("Bus type is not set up corretly," +
"please select either axi or bus")
#self.model.add_slave
return Box(position=position,
scene=scene,
name=name,
color=color,
select_func=self.box_select,
deselect_func=self.box_deselect,
user_data=ID)
def test_find_module_filename(self):
module_name = "wb_spi"
result = utils.find_module_filename(module_name, debug = self.dbg)
self.assertEqual(len(result) > 0, True)
def add_slave(self, name, slave_type, module_tags = {}, slave_project_tags = None, slave_index=-1):
#Adds a slave to the specified bus at the specified index.
if isinstance(slave_type, str):
slave_type = _string_to_slave_type(slave_type)
# Check if the slave_index makes sense. If slave index s -1 then add it
# to the next available location
#print "name: %s" % name
if name == "SDB":
return self.add_sdb()
if slave_project_tags is None:
slave_project_tags = {}
slave_project_tags["filename"] = utils.find_module_filename(module_tags["module"])
slave_project_tags["bind"] = {}
slave = None
module_ports = {}
if "ports" in module_tags:
#module_ports = cu.expand_ports(module_tags["ports"])
module_ports = module_tags["ports"]
bindings = {}
if "bind" in slave_project_tags:
bindings = cu.expand_user_constraints(slave_project_tags["bind"])
#Check to see if the project overrides the project_tags
self.gm.add_node( name,
NodeType.SLAVE,
slave_type,
project_tags = slave_project_tags,
module_tags = module_tags,
ports = module_ports,
bindings = bindings)
s_count = self.gm.get_number_of_slaves(slave_type)
#If the user didn't specify the slave index put it at the end
if slave_index == -1:
slave_index = s_count
else: # Add the slave wherever.
if slave_type == SlaveType.PERIPHERAL:
if slave_index == 0 and name != "SDB":
raise gm.SlaveError("Only the SDB can be at position 0")
s_count = self.gm.get_number_of_peripheral_slaves()
uname = get_unique_name(name,
NodeType.SLAVE,
slave_type,
s_count - 1)
slave = self.gm.get_node(uname)
if slave_index < s_count - 1:
self.gm.move_peripheral_slave(slave.slave_index,
slave_index)
elif slave_type == SlaveType.MEMORY:
s_count = self.gm.get_number_of_memory_slaves()
uname = get_unique_name(name,
NodeType.SLAVE,
slave_type,
s_count - 1)
slave = self.gm.get_node(uname)
if slave_index < s_count - 1:
self.gm.move_slave(slave.slave_index,
slave_index,
SlaveType.MEMORY)
def test_find_module_filename(self):
module_name = "wb_spi"
result = utils.find_module_filename(module_name, debug=self.dbg)
self.assertEqual(len(result) > 0, True)