def test(request, silent=True):
veriloggen.reset()
simtype = request.config.getoption('--sim')
rslt = onnx_matrix_add.run(a_shape, b_shape,
a_dtype, b_dtype, c_dtype,
par, axi_datawidth, silent,
filename=None, simtype=simtype,
outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out')
verify_rslt = rslt.splitlines()[-1]
assert(verify_rslt == '# verify: PASSED')
b_shape = (15, 15)
a_dtype = ng.int16
b_dtype = ng.int16
c_dtype = ng.int16
par = 4
axi_datawidth = 64
def test(request, silent=True):
veriloggen.reset()
simtype = request.config.getoption('--sim')
rslt = onnx_matrix_add.run(a_shape, b_shape,
a_dtype, b_dtype, c_dtype,
par, axi_datawidth, silent,
filename=None, simtype=simtype,
outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out')
verify_rslt = rslt.splitlines()[-1]
assert(verify_rslt == '# verify: PASSED')
if __name__ == '__main__':
rslt = onnx_matrix_add.run(a_shape, b_shape,
a_dtype, b_dtype, c_dtype,
par, axi_datawidth, silent=False,
filename='tmp.v',
outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out')
print(rslt)