def resp( type_, len, data ): msg = MemMsg(32,32).resp if type_ == 'rd': msg.type_ = MemRespMsg.TYPE_READ elif type_ == 'wr': msg.type_ = MemRespMsg.TYPE_WRITE msg.len = len msg.data = data return msg
def req( type_, addr, len, data ): msg = MemMsg(32,32).req if type_ == 'rd': msg.type_ = MemReqMsg.TYPE_READ elif type_ == 'wr': msg.type_ = MemReqMsg.TYPE_WRITE msg.addr = addr msg.len = len msg.data = data return msg
def __init__(s):
# Parameters
num_cores = 4
mopaque_nbits = 8
addr_nbits = 32
data_nbits = 32
cacheline_nbits = 128
# Interface
s.procifc = MemMsg(mopaque_nbits, addr_nbits, data_nbits)
s.mainmemifc = MemMsg(mopaque_nbits, addr_nbits, cacheline_nbits)
s.procreq = InValRdyBundle[num_cores](s.procifc.req)
s.procresp = OutValRdyBundle[num_cores](s.procifc.resp)
s.mainmemreq = OutValRdyBundle(s.mainmemifc.req)
s.mainmemresp = InValRdyBundle(s.mainmemifc.resp)
s.dcache_miss = OutPort(num_cores)
s.dcache_access = OutPort(num_cores)
# Connection
s.inner = McoreDataCacheVRTL_inner()
procreq_nbits = s.procifc.req.nbits
procresp_nbits = s.procifc.resp.nbits
for i in xrange(num_cores):
s.connect_pairs(
s.procreq[i].val,
s.inner.procreq_val[i],
s.procreq[i].rdy,
s.inner.procreq_rdy[i],
s.procreq[i].msg,
s.inner.procreq_msg[i * procreq_nbits:(i + 1) * procreq_nbits],
s.procresp[i].val,
s.inner.procresp_val[i],
s.procresp[i].rdy,
s.inner.procresp_rdy[i],
s.procresp[i].msg,
s.inner.procresp_msg[i * procresp_nbits:(i + 1) *
procresp_nbits],
s.mainmemreq,
s.inner.mainmemreq,
s.mainmemresp,
s.inner.mainmemresp,
s.dcache_miss,
s.inner.dcache_miss,
s.dcache_access,
s.inner.dcache_access,
)
def __init__(s, src_ptr, dest_ptr, nbytes, stall_prob, latency):
# Instantiate models
s.mcopy = MemCopy(MemMsg(32, 32), src_ptr, dest_ptr, nbytes)
s.mem = TestMemory(MemMsg(32, 32), 1, stall_prob, latency)
# Connect models
s.connect(s.mcopy.memreq, s.mem.reqs[0])
s.connect(s.mcopy.memresp, s.mem.resps[0])
def __init__(s, model, dump_vcd, num_cores=1, mem_stall=False):
num_memports = 2 # 1 dmem, 1 imem
data_nbits = 128 # 16B cacheline
# Instantiate models
s.model = model
if mem_stall:
s.mem = TestMemory(MemMsg(8, 32, data_nbits), num_memports, 0.5, 3)
else:
s.mem = TestMemory(MemMsg(8, 32, data_nbits), num_memports)
# Connect memory ports
s.connect(s.model.imemreq, s.mem.reqs[0])
s.connect(s.model.imemresp, s.mem.resps[0])
s.connect(s.model.dmemreq, s.mem.reqs[1])
s.connect(s.model.dmemresp, s.mem.resps[1])
# Bring stats_en, commit_inst, and proc2mngr up to the top level
# Also brings all statistic ports up
# About prog2mngr interface: Note simulator only gets output, so we
# don't need to worry about the mngr2proc interface. The simulator
# will monitor this interface for handling various message types.
s.proc2mngr = OutValRdyBundle(32)
if num_cores == 1:
s.connect(s.model.proc2mngr, s.proc2mngr)
else:
s.connect(s.model.proc2mngr[0], s.proc2mngr)
s.stats_en = OutPort(1)
s.commit_inst = OutPort(num_cores)
s.icache_miss = OutPort(num_cores)
s.icache_access = OutPort(num_cores)
s.dcache_miss = OutPort(num_cores)
s.dcache_access = OutPort(num_cores)
s.connect(s.model.stats_en, s.stats_en)
s.connect(s.model.commit_inst, s.commit_inst)
s.connect(s.model.icache_miss, s.icache_miss)
s.connect(s.model.icache_access, s.icache_access)
s.connect(s.model.dcache_miss, s.dcache_miss)
s.connect(s.model.dcache_access, s.dcache_access)
if dump_vcd:
s.model.vcd_file = dump_vcd
if hasattr(s.model, 'inner'):
s.model.inner.vcd_file = dump_vcd
def __init__(s):
# Parameters
num_reqers = 4 # 4 data caches
num_reqees = 1 # 1 memory port
num_ports = max(num_reqers, num_reqees) # We still have 4 ports
nopaque_nbits = 8
mopaque_nbits = 8
addr_nbits = 32
data_nbits = 128 # MemNet deals with 128 bit refill requests
# Interface
s.memifc = MemMsg(mopaque_nbits, addr_nbits, data_nbits)
s.mainmemifc = MemMsg(mopaque_nbits, addr_nbits, data_nbits)
s.memreq_val = InPort(4)
s.memreq_rdy = OutPort(4)
s.memreq_msg = InPort(s.memifc.req.nbits * 4)
s.memresp_val = OutPort(4)
s.memresp_rdy = InPort(4)
s.memresp_msg = OutPort(s.memifc.resp.nbits * 4)
s.mainmemreq_val = OutPort(4)
s.mainmemreq_rdy = InPort(4)
s.mainmemreq_msg = OutPort(s.mainmemifc.req.nbits * 4)
s.mainmemresp_val = InPort(4)
s.mainmemresp_rdy = OutPort(4)
s.mainmemresp_msg = InPort(s.mainmemifc.resp.nbits * 4)
# connect to Verilog module
s.set_ports({
'clk': s.clk,
'reset': s.reset,
'memreq_val': s.memreq_val,
'memreq_rdy': s.memreq_rdy,
'memreq_msg': s.memreq_msg,
'memresp_val': s.memresp_val,
'memresp_rdy': s.memresp_rdy,
'memresp_msg': s.memresp_msg,
'mainmemreq_val': s.mainmemreq_val,
'mainmemreq_rdy': s.mainmemreq_rdy,
'mainmemreq_msg': s.mainmemreq_msg,
'mainmemresp_val': s.mainmemresp_val,
'mainmemresp_rdy': s.mainmemresp_rdy,
'mainmemresp_msg': s.mainmemresp_msg,
})
def __init__(s):
# Parameters
num_reqers = 4 # 4 processors
num_reqees = 4 # 4 data caches
num_ports = max(num_reqers, num_reqees) # We still have 4 ports
nopaque_nbits = 8
mopaque_nbits = 8
addr_nbits = 32
data_nbits = 32 # CacheNet only deals with 32 bit requests
# Interface
s.procifc = MemMsg(mopaque_nbits, addr_nbits, data_nbits)
s.cacheifc = MemMsg(mopaque_nbits, addr_nbits, data_nbits)
s.procreq_val = InPort(4)
s.procreq_rdy = OutPort(4)
s.procreq_msg = InPort(s.procifc.req.nbits * 4)
s.procresp_val = OutPort(4)
s.procresp_rdy = InPort(4)
s.procresp_msg = OutPort(s.procifc.resp.nbits * 4)
s.cachereq_val = OutPort(4)
s.cachereq_rdy = InPort(4)
s.cachereq_msg = OutPort(s.cacheifc.req.nbits * 4)
s.cacheresp_val = InPort(4)
s.cacheresp_rdy = OutPort(4)
s.cacheresp_msg = InPort(s.cacheifc.resp.nbits * 4)
# connect to Verilog module
s.set_ports({
'clk': s.clk,
'reset': s.reset,
'procreq_val': s.procreq_val,
'procreq_rdy': s.procreq_rdy,
'procreq_msg': s.procreq_msg,
'procresp_val': s.procresp_val,
'procresp_rdy': s.procresp_rdy,
'procresp_msg': s.procresp_msg,
'cachereq_val': s.cachereq_val,
'cachereq_rdy': s.cachereq_rdy,
'cachereq_msg': s.cachereq_msg,
'cacheresp_val': s.cacheresp_val,
'cacheresp_rdy': s.cacheresp_rdy,
'cacheresp_msg': s.cacheresp_msg,
})
def __init__(s):
# Parameters
num_cores = 4
mopaque_nbits = 8
addr_nbits = 32
data_nbits = 32
cacheline_nbits = 128
# Interface
s.procifc = MemMsg(mopaque_nbits, addr_nbits, data_nbits)
s.mainmemifc = MemMsg(mopaque_nbits, addr_nbits, cacheline_nbits)
s.procreq_val = InPort(num_cores)
s.procreq_rdy = OutPort(num_cores)
s.procreq_msg = InPort(s.procifc.req.nbits * num_cores)
s.procresp_val = OutPort(num_cores)
s.procresp_rdy = InPort(num_cores)
s.procresp_msg = OutPort(s.procifc.resp.nbits * num_cores)
s.mainmemreq = OutValRdyBundle(s.mainmemifc.req)
s.mainmemresp = InValRdyBundle(s.mainmemifc.resp)
s.dcache_miss = OutPort(num_cores)
s.dcache_access = OutPort(num_cores)
# connect to Verilog module
s.set_ports({
'clk': s.clk,
'reset': s.reset,
'procreq_val': s.procreq_val,
'procreq_rdy': s.procreq_rdy,
'procreq_msg': s.procreq_msg,
'procresp_val': s.procresp_val,
'procresp_rdy': s.procresp_rdy,
'procresp_msg': s.procresp_msg,
'mainmemreq_val': s.mainmemreq.val,
'mainmemreq_rdy': s.mainmemreq.rdy,
'mainmemreq_msg': s.mainmemreq.msg,
'mainmemresp_val': s.mainmemresp.val,
'mainmemresp_rdy': s.mainmemresp.rdy,
'mainmemresp_msg': s.mainmemresp.msg,
'dcache_miss': s.dcache_miss,
'dcache_access': s.dcache_access,
})
def __init__(s, single_dest, mopaque_nbits, addr_nbits, data_nbits,
nopaque_nbits, num_nodes):
# Parameters
src_nbits = clog2(num_nodes)
#---------------------------------------------------------------------
# Interface
#---------------------------------------------------------------------
s.memifc = MemMsg(mopaque_nbits, addr_nbits, data_nbits)
s.netreqifc = NetMsg(num_nodes, 2**nopaque_nbits, s.memifc.req.nbits)
s.netrespifc = NetMsg(num_nodes, 2**nopaque_nbits, s.memifc.resp.nbits)
s.memreq = InValRdyBundle(s.memifc.req)
s.netreq = OutValRdyBundle(s.netreqifc)
s.memresp = OutValRdyBundle(s.memifc.resp)
s.netresp = InValRdyBundle(s.netrespifc)
s.src_id = InPort(src_nbits)
#---------------------------------------------------------------------
# Connections
#---------------------------------------------------------------------
s.connect(s.memreq.val, s.netreq.val)
s.connect(s.memreq.rdy, s.netreq.rdy)
s.connect(s.memresp.val, s.netresp.val)
s.connect(s.memresp.rdy, s.netresp.rdy)
# Modify memreq's opaque bit to add src information
s.temp_memreq = Wire(s.memifc.req)
s.connect(s.temp_memreq, s.netreq.msg.payload)
@s.combinational
def comb_req():
if single_dest:
s.netreq.msg.dest.value = 0
else:
s.netreq.msg.dest.value = s.memreq.msg.addr[
4:6] # hard code 4 bank for now
s.temp_memreq.value = s.memreq.msg
s.temp_memreq.opaque[mopaque_nbits -
src_nbits:mopaque_nbits].value = s.src_id
s.connect(s.netreq.msg.src, s.src_id)
s.connect(s.netreq.msg.opaque, 0)
# Clear the opaque field of memresp
@s.combinational
def comb_resp():
s.memresp.msg.value = s.netresp.msg.payload
s.memresp.msg.opaque[mopaque_nbits -
src_nbits:mopaque_nbits].value = 0
def __init__(s,
WordcountPRTL,
src_msgs,
sink_msgs,
stall_prob,
latency,
src_delay,
sink_delay,
dump_vcd=False,
test_verilog=False):
# Instantiate Models
s.src = TestSource(WordcountReqMsg(), src_msgs, src_delay)
s.wordcount = WordcountPRTL
s.sink = TestSink(WordcountRespMsg(), sink_msgs, sink_delay)
s.mem = TestMemory(MemMsg(8, 32, 32), 1, stall_prob, latency)
# Dump VCD
if dump_vcd:
s.wordcount.vcd_file = dump_vcd
# Translation
if test_verilog:
s.wordcount = TranslationTool(s.wordcount)
# Connect
s.connect(s.src.out, s.wordcount.wcreq)
s.connect(s.wordcount.wcresp, s.sink.in_)
s.connect(s.wordcount.memreq, s.mem.reqs[0])
s.connect(s.wordcount.memresp, s.mem.resps[0])
def __init__(s,
digitrecPRTL,
src_msgs,
sink_msgs,
stall_prob,
latency,
src_delay,
sink_delay,
dump_vcd=False,
test_verilog=False):
# Instantiate Models
s.src = TestSource(digitrecReqMsg(), src_msgs, src_delay)
s.di = digitrecPRTL
s.sink = TestSink(digitrecRespMsg(), sink_msgs, sink_delay)
s.mem = TestMemory(MemMsg(8, 32, 64), 1, stall_prob, latency)
# Dump VCD
if dump_vcd:
s.di.vcd_file = dump_vcd
# Translation
if test_verilog:
s.di = TranslationTool(s.di)
# Connect
s.connect(s.src.out, s.di.direq)
s.connect(s.di.diresp, s.sink.in_)
s.connect(s.di.memreq, s.mem.reqs[0])
s.connect(s.di.memresp, s.mem.resps[0])
def __init__(s,
SchedulerVRTL,
src_msgs,
sink_msgs,
stall_prob,
latency,
src_delay,
sink_delay,
dump_vcd=False,
test_verilog=False):
# Instantiate Models
s.src = TestSource(pageRankReqMsg(), src_msgs, src_delay)
s.di = SchedulerVRTL
s.sink = TestSink(pageRankRespMsg(), sink_msgs, sink_delay)
s.mem = TestMemory(MemMsg(8, 32, 32), 2, stall_prob, latency)
# Dump VCD
if dump_vcd:
s.di.vcd_file = dump_vcd
# Translation
if test_verilog:
s.di = TranslationTool(s.di)
# Connect
s.connect(s.src.out, s.di.direq)
s.connect(s.di.diresp, s.sink.in_)
s.connect(s.di.memreq[0], s.mem.reqs[0])
s.connect(s.di.memresp[0], s.mem.resps[0])
s.connect(s.di.memreq[1], s.mem.reqs[1])
s.connect(s.di.memresp[1], s.mem.resps[1])
def __init__(s):
# interface
s.in_control = InValRdyBundle(inst_msg()) # control word
s.memresp = InValRdyBundle(MemMsg(32, nWid).resp)
# 0,1: right/left neighbors
# 2,3: length-2 right/left PEs
# 4,5: length-4 right/left PEs
s.in_neighbor = InValRdyBundle[6](nWid)
s.memreq = OutValRdyBundle(MemMsg(32, nWid).req)
s.out_fsm = OutValRdyBundle(1) # response to FSM
s.out_neighbor = OutValRdyBundle[6](nWid)
# Queues
s.memreq_q = SingleElementBypassQueue(MemReqMsg(32, nWid))
s.connect(s.memreq, s.memreq_q.deq)
#s.memresp_q = SingleElementPipelinedQueue( MemRespMsg(16) )
s.memresp_q = SingleElementBypassQueue(MemRespMsg(nWid))
s.connect(s.memresp, s.memresp_q.enq)
# temporarily store destination for non-blocking loads
s.memdes_q = NormalQueue(nMemInst, nDesField)
# PE local register file
s.rf = RegisterFile(nWid, nReg, 2) # 2 read ports
# approx_mul
# input is done by reqMsg(src0, src1) done in control plane.
s.approx_mul = CombinationalApproxMult(nWid / 2, 4)
s.mul_msg = MymultReqMsg(nWid / 2)
# temporary variables
s.src0_tmp = Wire(nWid)
s.src1_tmp = Wire(nWid)
s.des_tmp = Wire(nWid)
s.go = Wire(1)
s.go_req = Wire(1)
s.go_resp = Wire(1)
s.go_mul = Wire(1)
s.reqsent = RegRst(1, 0)
def __init__(s):
# Instantiate models
s.src = TestSource(32, [], 0)
s.sink = TestSink(32, [], 0)
s.proc = ParcProcFL()
s.mem = TestMemory(MemMsg(32, 32), 3)
s.xcel = GenericXcelFL()
def __init__(s, lane_id, nmul_stages, mem_delay):
s.memreq_params = mem_msgs.MemReqParams(32, 32)
s.memresp_params = mem_msgs.MemRespParams(32)
s.mem = TestMemory(s.memreq_params, s.memresp_params, 1, mem_delay)
mem_ifc = MemMsg(32, 32)
cpu_ifc = CP2Msg(5, 32)
s.lane = DotProduct(mem_ifc, cpu_ifc)
def req(type_, addr, len, data):
msg = MemMsg(32, 32).req
if type_ == 'rd': msg.type_ = MemReqMsg.TYPE_READ
elif type_ == 'wr': msg.type_ = MemReqMsg.TYPE_WRITE
msg.addr = addr
msg.len = len
msg.data = data
return msg
def __init__(s, single_dest, mopaque_nbits, addr_nbits, data_nbits,
nopaque_nbits, num_nodes):
# Parameters
src_nbits = clog2(num_nodes)
#---------------------------------------------------------------------
# Interface
#---------------------------------------------------------------------
s.memifc = MemMsg(mopaque_nbits, addr_nbits, data_nbits)
s.netreqifc = NetMsg(num_nodes, 2**nopaque_nbits, s.memifc.req.nbits)
s.netrespifc = NetMsg(num_nodes, 2**nopaque_nbits, s.memifc.resp.nbits)
s.netreq = InValRdyBundle(s.netreqifc)
s.netresp = OutValRdyBundle(s.netrespifc)
s.memreq = OutValRdyBundle(s.memifc.req)
s.memresp = InValRdyBundle(s.memifc.resp)
s.src_id = InPort(src_nbits)
#---------------------------------------------------------------------
# Connections
#---------------------------------------------------------------------
s.connect(s.netreq.val, s.memreq.val)
s.connect(s.netreq.rdy, s.memreq.rdy)
s.connect(s.netresp.val, s.memresp.val)
s.connect(s.netresp.rdy, s.memresp.rdy)
# Just need to unpack netreq
s.connect(s.netreq.msg.payload, s.memreq.msg)
# For resp, need to pack memresp.msg with the header
s.connect(s.netresp.msg.src, s.src_id)
s.connect(s.netresp.msg.opaque, 0)
s.connect(s.netresp.msg.payload, s.memresp.msg)
# Use the hidden dest information to determine the recipient
@s.combinational
def comb_resp():
if single_dest:
s.netresp.msg.dest.value = 0
else:
s.netresp.msg.dest.value = s.memresp.msg.opaque[
mopaque_nbits - src_nbits:mopaque_nbits]
def __init__(s, src_msgs, sink_msgs, stall_prob, latency, src_delay,
sink_delay, dump_vcd):
# Here we assume 16B cacheline, so the bank bits are slice(4, 6)
# +--------------------------+--------------+--------+--------+--------+
# | 22b | 4b | 2b | 2b | 2b |
# | tag | index |bank idx| offset | subwd |
# +--------------------------+--------------+--------+--------+--------+
src_msg = [[], [], [], []]
sink_msg = [[], [], [], []]
for i in xrange(len(src_msgs)):
src_msg[src_msgs[i].addr[5:7].uint()].append(src_msgs[i])
sink_msg[src_msgs[i].addr[5:7].uint()].append(sink_msgs[i])
# Instantiate models
s.src = [
TestSource(MemReqMsg(8, 32, 32), src_msg[i], src_delay)
for i in xrange(4)
]
s.cachenet = CacheNetRTL()
s.mem = TestMemory(MemMsg(8, 32, 32), 4, stall_prob, latency)
s.sink = [
TestNetCacheSink(MemRespMsg(8, 32), sink_msg[i], sink_delay)
for i in xrange(4)
]
# Dump VCD
if dump_vcd:
s.cachenet.vcd_file = dump_vcd
if hasattr(s.cachenet, 'inner'):
s.cachenet.inner.vcd_file = dump_vcd
# s.cache.vcd_file = dump_vcd
# if hasattr(s.cache, 'inner'):
# s.cache.inner.vcd_file = dump_vcd
# Connect
for i in xrange(4):
s.connect(s.src[i].out, s.cachenet.procreq[i])
s.connect(s.sink[i].in_, s.cachenet.procresp[i])
for i in xrange(4):
s.connect(s.cachenet.cachereq[i], s.mem.reqs[i])
s.connect(s.cachenet.cacheresp[i], s.mem.resps[i])
def resp(type_, len, data):
msg = MemMsg(32, 32).resp
if type_ == 'rd': msg.type_ = MemRespMsg.TYPE_READ
elif type_ == 'wr': msg.type_ = MemRespMsg.TYPE_WRITE
msg.len = len
msg.data = data
return msg
def __init__( s ):
# Parameters
num_cores = 4
mopaque_nbits = 8
nopaque_nbits = 8
addr_nbits = 32
icache_nbytes = 256
dcache_nbytes = 256
data_nbits = 32
cacheline_nbits = 128
#---------------------------------------------------------------------
# Interface
#---------------------------------------------------------------------
s.memifc = MemMsg( mopaque_nbits, addr_nbits, cacheline_nbits )
s.mngr2proc = InValRdyBundle [num_cores]( 32 )
s.proc2mngr = OutValRdyBundle[num_cores]( 32 )
s.imemreq = OutValRdyBundle( s.memifc.req )
s.imemresp = InValRdyBundle ( s.memifc.resp )
s.dmemreq = OutValRdyBundle( s.memifc.req )
s.dmemresp = InValRdyBundle ( s.memifc.resp )
# These ports are for statistics. Basically we want to provide the
# simulator with some useful signals to let the simulator calculate
# cache miss rate.
s.stats_en = OutPort( 1 )
s.commit_inst = OutPort( 4 )
s.icache_miss = OutPort( 4 )
s.icache_access = OutPort( 4 )
s.dcache_miss = OutPort( 4 )
s.dcache_access = OutPort( 4 )
def __init__(s, pe_model, src_ctr_in_msgs, src_nbr_in_msgs,
sink_fsm_out_msgs, sink_nbr_out_msgs, src_delay, sink_delay):
# Instantiate models
#s.src_mem_in = TestSource (nWid, src_mem_in_msgs, src_delay)
s.src_ctr_in = TestSource(inst_msg(), src_ctr_in_msgs, src_delay)
s.src_nbr_in = [
TestSource(nWid, src_nbr_in_msgs[i], src_delay) for i in range(6)
]
#s.sink_mem_out = TestSink (nWid, sink_mem_out_msgs, sink_delay)
s.sink_fsm_out = TestSink(1, sink_fsm_out_msgs, sink_delay)
s.sink_nbr_out = [
TestSink(nWid, sink_nbr_out_msgs[i], sink_delay) for i in range(6)
]
# 32 bit mem_addr, 16 bit data
# Potentially, addr format: 0x01230000, 0x01230002, 0x01230004. each bit in addr corresponds
# to 1 byte of data. Since data is 16 bit = 2 bytes, address incr by 2 bits.
s.mem = TestMemory(MemMsg(32, nWid), 1, 0,
0) # nports, stall_prob, latency, mem_nbytes
s.pe = pe_model
def __init__(s, model, dump_vcd, num_cores, src_delay, sink_delay,
mem_stall_prob, mem_latency):
num_memports = 2 # 1 dmem, 1 imem
data_nbits = 128 # 16B cacheline
s.num_cores = num_cores
s.src = TestSource[num_cores](32, [], src_delay)
s.sink = TestSink[num_cores](32, [], sink_delay)
s.model = model
s.mem = TestMemory(MemMsg(8, 32, data_nbits), num_memports,
mem_stall_prob, mem_latency)
# Composition <-> Memory
s.connect(s.model.imemreq, s.mem.reqs[0])
s.connect(s.model.imemresp, s.mem.resps[0])
s.connect(s.model.dmemreq, s.mem.reqs[1])
s.connect(s.model.dmemresp, s.mem.resps[1])
# Processor <-> Proc/Mngr
if num_cores == 1: # Single-core system
s.connect(s.model.mngr2proc, s.src[0].out)
s.connect(s.model.proc2mngr, s.sink[0].in_)
else:
for i in xrange(num_cores):
s.connect(s.model.mngr2proc[i], s.src[i].out)
s.connect(s.model.proc2mngr[i], s.sink[i].in_)
# Dump VCD
if dump_vcd:
s.model.vcd_file = dump_vcd
if hasattr(s.model, 'inner'):
s.model.inner.vcd_file = dump_vcd
def __init__( s ):
# interface
s.in_control = InValRdyBundle (inst_msg() ) # control word
s.in_neighbor = InValRdyBundle[2] (nWid)
s.out_fsm = OutValRdyBundle (1) # response to FSM
s.out_neighbor = OutValRdyBundle[2] (nWid)
s.ocmreqs = OutValRdyBundle (MemMsg(8,32,nWid))
s.ocmresps = InValRdyBundle (MempMsg(8, nWid))
# PE local register file
s.rf = RegisterFile( nWid, nReg, 2, 1 )
# temporary variables
s.src0_tmp = Wire( nWid )
s.src1_tmp = Wire( nWid )
s.des_tmp = Wire( nWid )
s.go = Wire( 1 )
def __init__(s, nports, src_msgs, sink_msgs, stall_prob, latency,
src_delay, sink_delay):
# Messge type
mem_msgs = MemMsg(32, 32)
# Instantiate models
s.srcs = []
for i in range(nports):
s.srcs.append(TestSource(mem_msgs.req, src_msgs[i], src_delay))
s.mem = TestMemory(mem_msgs, nports, stall_prob, latency)
s.sinks = []
for i in range(nports):
s.sinks.append(TestSink(mem_msgs.resp, sink_msgs[i], sink_delay))
# Connect
for i in range(nports):
s.connect(s.srcs[i].out, s.mem.reqs[i])
s.connect(s.sinks[i].in_, s.mem.resps[i])
def __init__(s, mem_ifc_types=MemMsg(32, 32)):
# Interface
s.xcelreq = InValRdyBundle(XcelReqMsg())
s.xcelresp = OutValRdyBundle(XcelRespMsg())
#s.memreq = InValRdyBundle ( mem_ifc_types.req )
#s.memresp = OutValRdyBundle ( mem_ifc_types.resp )
# Adapters
s.xcelreq_q = InValRdyQueueAdapter(s.xcelreq)
s.xcelresp_q = OutValRdyQueueAdapter(s.xcelresp)
# Accelerator registers
s.xregs = [Bits(32, 0) for _ in xrange(32)]
# Concurrent block
@s.tick_fl
def block():
# We loop forever handling accelerator requests.
while True:
xcelreq_msg = s.xcelreq_q.popleft()
if xcelreq_msg.type_ == XcelReqMsg.TYPE_READ:
data = s.xregs[xcelreq_msg.raddr]
s.xcelresp_q.append(XcelRespMsg().mk_rd(data))
else:
s.xregs[xcelreq_msg.raddr] = xcelreq_msg.data
s.xcelresp_q.append(XcelRespMsg().mk_wr())
def mreq(a):
return MemMsg(32, 32).req.mk_msg(0, a, 0, 0)
def __init__( s, reset_vector=0, test_en=True ):
s.reset_vector = reset_vector
s.test_en = test_en
# Proc/Mngr Interface
s.mngr2proc = InValRdyBundle( 32 )
s.proc2mngr = OutValRdyBundle( 32 )
# Instruction Memory Request/Response Interface
s.imemreq = OutValRdyBundle ( MemReqMsg(32,32) )
s.imemresp = InValRdyBundle ( MemRespMsg(32) )
# Data Memory Request/Response Interface
s.dmemreq = OutValRdyBundle ( MemReqMsg(32,32) )
s.dmemresp = InValRdyBundle ( MemRespMsg(32) )
# Accelerator Interface
s.xcelreq = OutValRdyBundle( XcelReqMsg() )
s.xcelresp = InValRdyBundle( XcelRespMsg() )
# Extra Interface
s.go = InPort ( 1 )
s.status = OutPort ( 32 )
s.stats_en = OutPort ( 1 )
s.num_insts = OutPort ( 32 )
# Queue Adapters
s.mngr2proc_q = InValRdyQueueAdapter ( s.mngr2proc )
s.proc2mngr_q = OutValRdyQueueAdapter ( s.proc2mngr )
s.imemreq_q = OutValRdyQueueAdapter ( s.imemreq )
s.imemresp_q = InValRdyQueueAdapter ( s.imemresp )
s.dmemreq_q = OutValRdyQueueAdapter ( s.dmemreq )
s.dmemresp_q = InValRdyQueueAdapter ( s.dmemresp )
s.xcelreq_q = OutValRdyQueueAdapter ( s.xcelreq )
s.xcelresp_q = InValRdyQueueAdapter ( s.xcelresp )
# Helpers to make memory read/write requests
mem_ifc_types = MemMsg(32,32)
s.mk_rd = mem_ifc_types.req.mk_rd
s.mk_wr = mem_ifc_types.req.mk_wr
# Pipeline queues
s.pc_queue_FX = Queue(4)
s.inst_queue_XW = Queue(4)
s.wb_queue_XW = Queue(4)
s.R = ParcProcCL.RegisterFile()
s.stall_X = False
s.stall_W = False
s.stall_type_X = " "
s.stall_type_W = " "
s.WB_NONE = 0
s.WB_REGWR = 1
s.ifetch_wait = 0
# Reset
s.reset_proc()
def __init__(s):
# Parameters
num_reqers = 4 # 4 processors
num_reqees = 4 # 4 data caches
num_ports = max(num_reqers, num_reqees) # We still have 4 ports
nopaque_nbits = 8
mopaque_nbits = 8
addr_nbits = 32
data_nbits = 32 # CacheNet only deals with 32 bit requests
# Interface
s.procifc = MemMsg(mopaque_nbits, addr_nbits, data_nbits)
s.cacheifc = MemMsg(mopaque_nbits, addr_nbits, data_nbits)
s.procreq = InValRdyBundle[num_ports](s.procifc.req)
s.procresp = OutValRdyBundle[num_ports](s.procifc.resp)
s.cachereq = OutValRdyBundle[num_ports](s.cacheifc.req)
s.cacheresp = InValRdyBundle[num_ports](s.cacheifc.resp)
# Connection
s.inner = CacheNetVRTL_inner()
procreq_nbits = s.procifc.req.nbits
procresp_nbits = s.procifc.resp.nbits
cachereq_nbits = s.cacheifc.req.nbits
cacheresp_nbits = s.cacheifc.resp.nbits
for i in xrange(num_ports):
s.connect_pairs(
s.procreq[i].val,
s.inner.procreq_val[i],
s.procreq[i].rdy,
s.inner.procreq_rdy[i],
s.procreq[i].msg,
s.inner.procreq_msg[i * procreq_nbits:(i + 1) * procreq_nbits],
s.procresp[i].val,
s.inner.procresp_val[i],
s.procresp[i].rdy,
s.inner.procresp_rdy[i],
s.procresp[i].msg,
s.inner.procresp_msg[i * procresp_nbits:(i + 1) *
procresp_nbits],
s.cachereq[i].val,
s.inner.cachereq_val[i],
s.cachereq[i].rdy,
s.inner.cachereq_rdy[i],
s.cachereq[i].msg,
s.inner.cachereq_msg[i * cachereq_nbits:(i + 1) *
cachereq_nbits],
s.cacheresp[i].val,
s.inner.cacheresp_val[i],
s.cacheresp[i].rdy,
s.inner.cacheresp_rdy[i],
s.cacheresp[i].msg,
s.inner.cacheresp_msg[i * cacheresp_nbits:(i + 1) *
cacheresp_nbits],
)
def __init__(s):
# Parameters
num_cores = 1
opaque_nbits = 8
addr_nbits = 32
icache_nbytes = 256
dcache_nbytes = 256
data_nbits = 32
cacheline_nbits = 128
#---------------------------------------------------------------------
# Interface
#---------------------------------------------------------------------
s.memifc = MemMsg(opaque_nbits, addr_nbits, cacheline_nbits)
s.mngr2proc = InValRdyBundle(32)
s.proc2mngr = OutValRdyBundle(32)
s.imemreq = OutValRdyBundle(s.memifc.req)
s.imemresp = InValRdyBundle(s.memifc.resp)
s.dmemreq = OutValRdyBundle(s.memifc.req)
s.dmemresp = InValRdyBundle(s.memifc.resp)
# These ports are for statistics. Basically we want to provide the
# simulator with some useful signals to let the simulator calculate
# cache miss rate.
s.stats_en = OutPort(1)
s.commit_inst = OutPort(1)
s.icache_miss = OutPort(1)
s.icache_access = OutPort(1)
s.dcache_miss = OutPort(1)
s.dcache_access = OutPort(1)
#---------------------------------------------------------------------
# Verilog import
#---------------------------------------------------------------------
s.set_params({'dummy': 0})
# connect to Verilog module
s.set_ports({
'clk': s.clk,
'reset': s.reset,
'mngr2proc_msg': s.mngr2proc.msg,
'mngr2proc_val': s.mngr2proc.val,
'mngr2proc_rdy': s.mngr2proc.rdy,
'proc2mngr_msg': s.proc2mngr.msg,
'proc2mngr_val': s.proc2mngr.val,
'proc2mngr_rdy': s.proc2mngr.rdy,
'imemreq_msg': s.imemreq.msg,
'imemreq_val': s.imemreq.val,
'imemreq_rdy': s.imemreq.rdy,
'imemresp_msg': s.imemresp.msg,
'imemresp_val': s.imemresp.val,
'imemresp_rdy': s.imemresp.rdy,
'dmemreq_msg': s.dmemreq.msg,
'dmemreq_val': s.dmemreq.val,
'dmemreq_rdy': s.dmemreq.rdy,
'dmemresp_msg': s.dmemresp.msg,
'dmemresp_val': s.dmemresp.val,
'dmemresp_rdy': s.dmemresp.rdy,
'stats_en': s.stats_en,
'commit_inst': s.commit_inst,
'icache_miss': s.icache_miss,
'icache_access': s.icache_access,
'dcache_miss': s.dcache_miss,
'dcache_access': s.dcache_access,
})
def __init__(s):
# Parameters
num_cores = 4
mopaque_nbits = 8
addr_nbits = 32
cacheline_nbits = 128
# Interface
s.memifc = MemMsg(mopaque_nbits, addr_nbits, cacheline_nbits)
s.mngr2proc_val = InPort(num_cores)
s.mngr2proc_rdy = OutPort(num_cores)
s.mngr2proc_msg = InPort(32 * num_cores)
s.proc2mngr_val = OutPort(num_cores)
s.proc2mngr_rdy = InPort(num_cores)
s.proc2mngr_msg = OutPort(32 * num_cores)
s.imemreq = OutValRdyBundle(s.memifc.req)
s.imemresp = InValRdyBundle(s.memifc.resp)
s.dmemreq = OutValRdyBundle(s.memifc.req)
s.dmemresp = InValRdyBundle(s.memifc.resp)
s.stats_en = OutPort(1)
s.commit_inst = OutPort(num_cores)
s.icache_miss = OutPort(num_cores)
s.icache_access = OutPort(num_cores)
s.dcache_miss = OutPort(num_cores)
s.dcache_access = OutPort(num_cores)
# connect to Verilog module
s.set_ports({
'clk': s.clk,
'reset': s.reset,
'mngr2proc_val': s.mngr2proc_val,
'mngr2proc_rdy': s.mngr2proc_rdy,
'mngr2proc_msg': s.mngr2proc_msg,
'proc2mngr_val': s.proc2mngr_val,
'proc2mngr_rdy': s.proc2mngr_rdy,
'proc2mngr_msg': s.proc2mngr_msg,
'imemreq_val': s.imemreq.val,
'imemreq_rdy': s.imemreq.rdy,
'imemreq_msg': s.imemreq.msg,
'imemresp_val': s.imemresp.val,
'imemresp_rdy': s.imemresp.rdy,
'imemresp_msg': s.imemresp.msg,
'dmemreq_val': s.dmemreq.val,
'dmemreq_rdy': s.dmemreq.rdy,
'dmemreq_msg': s.dmemreq.msg,
'dmemresp_val': s.dmemresp.val,
'dmemresp_rdy': s.dmemresp.rdy,
'dmemresp_msg': s.dmemresp.msg,
'stats_en': s.stats_en,
'commit_inst': s.commit_inst,
'icache_miss': s.icache_miss,
'icache_access': s.icache_access,
'dcache_miss': s.dcache_miss,
'dcache_access': s.dcache_access,
})
def __init__(s):
# Parameters
num_cores = 4
mopaque_nbits = 8
addr_nbits = 32
cacheline_nbits = 128
# Interface
s.memifc = MemMsg(mopaque_nbits, addr_nbits, cacheline_nbits)
s.mngr2proc = InValRdyBundle[num_cores](32)
s.proc2mngr = OutValRdyBundle[num_cores](32)
s.imemreq = OutValRdyBundle(s.memifc.req)
s.imemresp = InValRdyBundle(s.memifc.resp)
s.dmemreq = OutValRdyBundle(s.memifc.req)
s.dmemresp = InValRdyBundle(s.memifc.resp)
# These ports are for statistics. Basically we want to provide the
# simulator with some useful signals to let the simulator calculate
# cache miss rate.
s.stats_en = OutPort(1)
s.commit_inst = OutPort(num_cores)
s.icache_miss = OutPort(num_cores)
s.icache_access = OutPort(num_cores)
s.dcache_miss = OutPort(num_cores)
s.dcache_access = OutPort(num_cores)
# Connection
s.inner = MultiCoreVRTL_inner()
memreq_nbits = s.memifc.req.nbits
memresp_nbits = s.memifc.resp.nbits
for i in xrange(num_cores):
s.connect_pairs(
s.mngr2proc[i].val,
s.inner.mngr2proc_val[i],
s.mngr2proc[i].rdy,
s.inner.mngr2proc_rdy[i],
s.mngr2proc[i].msg,
s.inner.mngr2proc_msg[i * 32:(i + 1) * 32],
s.proc2mngr[i].val,
s.inner.proc2mngr_val[i],
s.proc2mngr[i].rdy,
s.inner.proc2mngr_rdy[i],
s.proc2mngr[i].msg,
s.inner.proc2mngr_msg[i * 32:(i + 1) * 32],
s.imemreq,
s.inner.imemreq,
s.imemresp,
s.inner.imemresp,
s.dmemreq,
s.inner.dmemreq,
s.dmemresp,
s.inner.dmemresp,
s.stats_en,
s.inner.stats_en,
s.commit_inst,
s.inner.commit_inst,
s.icache_miss,
s.inner.icache_miss,
s.icache_access,
s.inner.icache_access,
s.dcache_miss,
s.inner.dcache_miss,
s.dcache_access,
s.inner.dcache_access,
)
def __init__(s,
mem_ifc_dtypes=MemMsg(32, 32),
nports=1,
stall_prob=0,
latency=0,
mem_nbytes=2**20):
# Interface
xr = range
s.reqs = [InValRdyBundle(mem_ifc_dtypes.req) for _ in xr(nports)]
s.resps = [OutValRdyBundle(mem_ifc_dtypes.resp) for _ in xr(nports)]
# Checks
assert mem_ifc_dtypes.req.data.nbits % 8 == 0
assert mem_ifc_dtypes.resp.data.nbits % 8 == 0
# Buffers to hold memory request/response messages
s.reqs_q = []
for req in s.reqs:
s.reqs_q.append(InValRdyRandStallAdapter(req, stall_prob))
s.resps_q = []
for resp in s.resps:
s.resps_q.append(OutValRdyInelasticPipeAdapter(resp, latency))
# Actual memory
s.mem = bytearray(mem_nbytes)
# Local constants
s.mem_ifc_dtypes = mem_ifc_dtypes
s.nports = nports
#---------------------------------------------------------------------
# Tick
#---------------------------------------------------------------------
@s.tick_cl
def tick():
# Tick adapters
for req_q, resp_q in zip(s.reqs_q, s.resps_q):
req_q.xtick()
resp_q.xtick()
# Iterate over input/output queues
for req_q, resp_q in zip(s.reqs_q, s.resps_q):
if not req_q.empty() and not resp_q.full():
# Dequeue memory request message
memreq = req_q.deq()
# When len is zero, then we use all of the data
nbytes = memreq.len
if memreq.len == 0:
nbytes = s.mem_ifc_dtypes.req.data.nbits / 8
# Handle a read request
if memreq.type_ == MemReqMsg.TYPE_READ:
# Copy the bytes from the bytearray into read data bits
read_data = Bits(s.mem_ifc_dtypes.req.data.nbits)
for j in range(nbytes):
read_data[j * 8:j * 8 + 8] = s.mem[memreq.addr + j]
# Create and enqueu response message
memresp = s.mem_ifc_dtypes.resp()
memresp.type_ = MemRespMsg.TYPE_READ
memresp.len = memreq.len
memresp.data = read_data
resp_q.enq(memresp)
# Handle a write request
elif memreq.type_ == MemReqMsg.TYPE_WRITE:
# Copy write data bits into bytearray
write_data = memreq.data
for j in range(nbytes):
s.mem[memreq.addr + j] = write_data[j * 8:j * 8 +
8].uint()
# Create and enqueu response message
memresp = s.mem_ifc_dtypes.resp()
memresp.type_ = MemRespMsg.TYPE_WRITE
memresp.len = 0
memresp.data = 0
resp_q.enq(memresp)
