def __init__(s, num_cores=1):
#---------------------------------------------------------------------
# Interface
#---------------------------------------------------------------------
# Starting F16 we turn core_id into input ports to
# enable module reusability. In the past it was passed as arguments.
s.core_id = InPort(32)
# Proc/Mngr Interface
s.mngr2proc = InValRdyBundle(32)
s.proc2mngr = OutValRdyBundle(32)
# Instruction Memory Request/Response Interface
s.imemreq = OutValRdyBundle(MemReqMsg4B)
s.imemresp = InValRdyBundle(MemRespMsg4B)
# Data Memory Request/Response Interface
s.dmemreq = OutValRdyBundle(MemReqMsg4B)
s.dmemresp = InValRdyBundle(MemRespMsg4B)
# val_W port used for counting commited insts.
s.commit_inst = OutPort(1)
# stats_en
s.stats_en = OutPort(1)
def __init__(s, payload_nbits=32):
# Parameters
# Your design does not need to support other values
nrouters = 4
opaque_nbits = 8
srcdest_nbits = clog2(nrouters)
# Interface
s.router_id = InPort(srcdest_nbits)
msg_type = NetMsg(nrouters, 2**opaque_nbits, payload_nbits)
s.in0 = InValRdyBundle(msg_type)
s.in1 = InValRdyBundle(msg_type)
s.in2 = InValRdyBundle(msg_type)
s.out0 = OutValRdyBundle(msg_type)
s.out1 = OutValRdyBundle(msg_type)
s.out2 = OutValRdyBundle(msg_type)
# Components
s.dpath = RouterDpathPRTL(payload_nbits)
s.ctrl = RouterCtrlPRTL()
s.connect(s.ctrl.router_id, s.router_id)
def __init__(s):
s.xcelreq = InValRdyBundle(XcelReqMsg())
s.xcelresp = OutValRdyBundle(XcelRespMsg())
s.memreq = OutValRdyBundle(MemReqMsg(8, 32, 32))
s.memresp = InValRdyBundle(MemRespMsg(8, 32))
s.reqcon = MemReqConnector(18, 8)
s.xcel = SortXcelHLS()
s.connect(s.xcelreq, s.xcel.xcelreq)
s.connect(s.xcelresp, s.xcel.xcelresp)
s.pq = SingleElementPipelinedQueue(MemRespMsg(8, 32))
s.connect(s.memresp, s.pq.enq)
s.connect(s.pq.deq, s.xcel.memresp)
s.bq = SingleElementBypassQueue(MemReqMsg(8, 32, 32))
s.connect(s.bq.deq, s.memreq)
s.connect(s.xcel.memreq.val, s.bq.enq.val)
s.connect(s.xcel.memreq.rdy, s.bq.enq.rdy)
s.connect(s.reqcon.in_, s.xcel.memreq)
s.connect(s.reqcon.out, s.bq.enq)
def __init__( s, num_banks=0 ):
# Parameters
idx_shamt = clog2( num_banks ) if num_banks > 0 else 0
size = 256 # 256 bytes
opaque_nbits = 8 # 8-bit opaque field
addr_nbits = 32 # 32-bit address
data_nbits = 32 # 32-bit data access
cacheline_nbits = 128 # 128-bit cacheline
#---------------------------------------------------------------------
# Interface
#---------------------------------------------------------------------
# Proc <-> Cache
s.cachereq = InValRdyBundle ( MemReqMsg(opaque_nbits, addr_nbits, data_nbits) )
s.cacheresp = OutValRdyBundle( MemRespMsg(opaque_nbits, data_nbits) )
# Cache <-> Mem
s.memreq = OutValRdyBundle( MemReqMsg(opaque_nbits, addr_nbits, cacheline_nbits) )
s.memresp = InValRdyBundle ( MemRespMsg(opaque_nbits, cacheline_nbits) )
s.ctrl = BlockingCacheBaseCtrlPRTL ( idx_shamt )
s.dpath = BlockingCacheBaseDpathPRTL( idx_shamt )
def __init__(s, single_dest, mopaque_nbits, addr_nbits, data_nbits,
nopaque_nbits, num_nodes):
# Parameters
src_nbits = clog2(num_nodes)
#---------------------------------------------------------------------
# Interface
#---------------------------------------------------------------------
s.memifc = MemMsg(mopaque_nbits, addr_nbits, data_nbits)
s.netreqifc = NetMsg(num_nodes, 2**nopaque_nbits, s.memifc.req.nbits)
s.netrespifc = NetMsg(num_nodes, 2**nopaque_nbits, s.memifc.resp.nbits)
s.memreq = InValRdyBundle(s.memifc.req)
s.netreq = OutValRdyBundle(s.netreqifc)
s.memresp = OutValRdyBundle(s.memifc.resp)
s.netresp = InValRdyBundle(s.netrespifc)
s.src_id = InPort(src_nbits)
#---------------------------------------------------------------------
# Connections
#---------------------------------------------------------------------
s.connect(s.memreq.val, s.netreq.val)
s.connect(s.memreq.rdy, s.netreq.rdy)
s.connect(s.memresp.val, s.netresp.val)
s.connect(s.memresp.rdy, s.netresp.rdy)
# Modify memreq's opaque bit to add src information
s.temp_memreq = Wire(s.memifc.req)
s.connect(s.temp_memreq, s.netreq.msg.payload)
@s.combinational
def comb_req():
if single_dest:
s.netreq.msg.dest.value = 0
else:
s.netreq.msg.dest.value = s.memreq.msg.addr[
4:6] # hard code 4 bank for now
s.temp_memreq.value = s.memreq.msg
s.temp_memreq.opaque[mopaque_nbits -
src_nbits:mopaque_nbits].value = s.src_id
s.connect(s.netreq.msg.src, s.src_id)
s.connect(s.netreq.msg.opaque, 0)
# Clear the opaque field of memresp
@s.combinational
def comb_resp():
s.memresp.msg.value = s.netresp.msg.payload
s.memresp.msg.opaque[mopaque_nbits -
src_nbits:mopaque_nbits].value = 0
def __init__(s, num_banks=0):
# Proc <-> Cache
s.cachereq = InValRdyBundle(MemReqMsg4B)
s.cacheresp = OutValRdyBundle(MemRespMsg4B)
# Cache <-> Mem
s.memreq = OutValRdyBundle(MemReqMsg16B)
s.memresp = InValRdyBundle(MemRespMsg16B)
# connect to Verilog module
s.set_params({'p_num_banks': num_banks})
s.set_ports({
'clk': s.clk,
'reset': s.reset,
'cachereq_msg': s.cachereq.msg,
'cachereq_val': s.cachereq.val,
'cachereq_rdy': s.cachereq.rdy,
'cacheresp_msg': s.cacheresp.msg,
'cacheresp_val': s.cacheresp.val,
'cacheresp_rdy': s.cacheresp.rdy,
'memreq_msg': s.memreq.msg,
'memreq_val': s.memreq.val,
'memreq_rdy': s.memreq.rdy,
'memresp_msg': s.memresp.msg,
'memresp_val': s.memresp.val,
'memresp_rdy': s.memresp.rdy,
})
def __init__( s, nbits = 8, nports = 1, bw = 32, n = 8, ):
#---------------------------------------------------------------------------
# Interface
#---------------------------------------------------------------------------
s.direq = InValRdyBundle ( pageRankReqMsg() )
s.diresp = OutValRdyBundle ( pageRankRespMsg() )
s.memreq = OutValRdyBundle ( MemReqMsg(8,32,32) )
s.memresp = InValRdyBundle ( MemRespMsg(8,32) )
#---------------------------------------------------------------------------
# Verilog import setup
#---------------------------------------------------------------------------
# verilog parameters
s.set_params({
'nbits' : nbits,
'nports' : nports,
'bw' : bw,
'n' : n
})
# verilog ports
s.set_ports({
'clk' : s.clk,
'reset' : s.reset,
# 'in_req_val' : s.direq.val,
# 'out_req_rdy' : s.direq.rdy,
# 'in_type' : s.direq.msg.type_,
# 'in_addr' : s.direq.msg.addr,
# 'in_data' : s.direq.msg.data,
# 'out_resp_val' : s.diresp.val,
# 'in_resp_rdy' : s.diresp.rdy,
# 'out_type' : s.diresp.msg.type_,
# 'out_data' : s.diresp.msg.data,
'pr_req_msg' : s.direq.msg,
'pr_req_val' : s.direq.val,
'pr_req_rdy' : s.direq.rdy,
'pr_resp_msg' : s.diresp.msg,
'pr_resp_val' : s.diresp.val,
'pr_resp_rdy' : s.diresp.rdy,
'mem_req_msg' : s.memreq.msg,
'mem_req_val' : s.memreq.val,
'mem_req_rdy' : s.memreq.rdy,
'mem_resp_msg' : s.memresp.msg,
'mem_resp_val' : s.memresp.val,
'mem_resp_rdy' : s.memresp.rdy,
})
def __init__(s, nbits=32, nports=2, n=8):
#---------------------------------------------------------------------------
# Interface
#---------------------------------------------------------------------------
s.direq = InValRdyBundle(pageRankReqMsg())
s.diresp = OutValRdyBundle(pageRankRespMsg())
s.memreq = [
OutValRdyBundle(MemReqMsg(8, 32, 32)) for _ in range(nports)
]
s.memresp = [InValRdyBundle(MemRespMsg(8, 32)) for _ in range(nports)]
#---------------------------------------------------------------------------
# Verilog import setup
#---------------------------------------------------------------------------
# verilog parameters
s.set_params({'nbits': nbits, 'nports': nports, 'n': n})
# verilog ports
s.set_ports({
'clk': s.clk,
'reset': s.reset,
# 'in_req_val' : s.direq.val,
# 'out_req_rdy' : s.direq.rdy,
# 'in_type' : s.direq.msg.type_,
# 'in_addr' : s.direq.msg.addr,
# 'in_data' : s.direq.msg.data,
# 'out_resp_val' : s.diresp.val,
# 'in_resp_rdy' : s.diresp.rdy,
# 'out_type' : s.diresp.msg.type_,
# 'out_data' : s.diresp.msg.data,
'in_req_msg': s.direq.msg,
'in_req_val': s.direq.val,
'in_req_rdy': s.direq.rdy,
'out_resp_msg': s.diresp.msg,
'out_resp_val': s.diresp.val,
'out_resp_rdy': s.diresp.rdy,
'mem_req0_msg': s.memreq[0].msg,
'mem_req0_val': s.memreq[0].val,
'mem_req0_rdy': s.memreq[0].rdy,
'mem_resp0_msg': s.memresp[0].msg,
'mem_resp0_val': s.memresp[0].val,
'mem_resp0_rdy': s.memresp[0].rdy,
'mem_req1_msg': s.memreq[1].msg,
'mem_req1_val': s.memreq[1].val,
'mem_req1_rdy': s.memreq[1].rdy,
'mem_resp1_msg': s.memresp[1].msg,
'mem_resp1_val': s.memresp[1].val,
'mem_resp1_rdy': s.memresp[1].rdy,
})
def __init__(s, single_dest, mopaque_nbits, addr_nbits, data_nbits,
nopaque_nbits, num_nodes):
# Parameters
src_nbits = clog2(num_nodes)
#---------------------------------------------------------------------
# Interface
#---------------------------------------------------------------------
s.memifc = MemMsg(mopaque_nbits, addr_nbits, data_nbits)
s.netreqifc = NetMsg(num_nodes, 2**nopaque_nbits, s.memifc.req.nbits)
s.netrespifc = NetMsg(num_nodes, 2**nopaque_nbits, s.memifc.resp.nbits)
s.netreq = InValRdyBundle(s.netreqifc)
s.netresp = OutValRdyBundle(s.netrespifc)
s.memreq = OutValRdyBundle(s.memifc.req)
s.memresp = InValRdyBundle(s.memifc.resp)
s.src_id = InPort(src_nbits)
#---------------------------------------------------------------------
# Connections
#---------------------------------------------------------------------
s.connect(s.netreq.val, s.memreq.val)
s.connect(s.netreq.rdy, s.memreq.rdy)
s.connect(s.netresp.val, s.memresp.val)
s.connect(s.netresp.rdy, s.memresp.rdy)
# Just need to unpack netreq
s.connect(s.netreq.msg.payload, s.memreq.msg)
# For resp, need to pack memresp.msg with the header
s.connect(s.netresp.msg.src, s.src_id)
s.connect(s.netresp.msg.opaque, 0)
s.connect(s.netresp.msg.payload, s.memresp.msg)
# Use the hidden dest information to determine the recipient
@s.combinational
def comb_resp():
if single_dest:
s.netresp.msg.dest.value = 0
else:
s.netresp.msg.dest.value = s.memresp.msg.opaque[
mopaque_nbits - src_nbits:mopaque_nbits]
def __init__(s, nbits=6, k=3):
# Interface
s.req = InValRdyBundle(FindMaxReqMsg())
s.resp = OutValRdyBundle(FindMaxRespMsg())
# Instantiate datapath and control
s.dpath = FindMaxDpathRTL(nbits, k=3)
s.ctrl = FindMaxCtrlRTL(nbits, k=3)
# connect input interface to dpath/ctrl
s.connect(s.req.msg.data, s.dpath.req_msg_data)
s.connect(s.req.val, s.ctrl.req_val)
s.connect(s.resp.rdy, s.ctrl.resp_rdy)
# connect dpath/ctrl to output interface
s.connect(s.dpath.resp_msg_data, s.resp.msg.data)
s.connect(s.dpath.resp_msg_idx, s.resp.msg.idx)
s.connect(s.ctrl.req_rdy, s.req.rdy)
s.connect(s.ctrl.resp_val, s.resp.val)
# connect dpath/ctrl
s.connect(s.dpath.isLarger, s.ctrl.isLarger)
s.connect(s.ctrl.max_reg_en, s.dpath.max_reg_en)
s.connect(s.ctrl.idx_reg_en, s.dpath.idx_reg_en)
s.connect(s.ctrl.knn_mux_sel, s.dpath.knn_mux_sel)
s.connect(s.ctrl.knn_counter, s.dpath.knn_counter)
def __init__(s, mem_ifc_types, src_ptr, dest_ptr, nbytes):
s.src_ptr = src_ptr
s.dest_ptr = dest_ptr
s.nbytes = nbytes
s.done = False
# Memory request/response ports
s.memreq = InValRdyBundle(mem_ifc_types.req)
s.memresp = OutValRdyBundle(mem_ifc_types.resp)
# BytesMemPortAdapter object
s.mem = BytesMemPortAdapter(s.memreq, s.memresp)
# This looks like a regular tick block, but because it is a
# pausable_tick there is something more sophisticated is going on.
# The first time we call the tick, the mem_copy function will try to
# ready from memory. This will get proxied to the BytesMemPortAdapter
# which will create a memory request and send it out the memreq port.
# Since we do not have the data yet, we cannot return the data to the
# mem_copy function so instead we use greenlets to switch back to the
# pausable tick function. The next time we call tick we jump back
# into the BytesMemPortAdapter object to see if the response has
# returned. When the response eventually returns, the
# BytesMemPortAdapter object will return the data and the underlying
# mem_copy function will move onto writing the memory.
@s.tick_fl
def logic():
if not s.reset:
mem_copy(s.mem, s.src_ptr, s.dest_ptr, s.nbytes)
s.done = True
def __init__(s, dtype, idx, synch_info):
s.in_ = InValRdyBundle(dtype)
s.out = OutValRdyBundle(dtype)
s.connect(s.out.msg, s.in_.msg)
s.num_cycles = Wire(32)
@s.combinational
def comb():
# PyMTL sensitivity bug... Force this combinational block to be
# fired every cycle.
_ = s.num_cycles
if synch_info.can_send_more_tokens(idx):
s.in_.rdy.value = s.out.rdy
s.out.val.value = s.in_.val
else:
s.in_.rdy.value = 0
s.out.val.value = 0
@s.tick
def tick():
if s.out.val and s.out.rdy:
synch_info.token_sent(idx)
s.num_cycles.next = s.num_cycles + 1
def __init__( s ):
# Interface
s.req = InValRdyBundle ( GcdUnitReqMsg() )
s.resp = OutValRdyBundle ( Bits(16) )
# Adapters
s.req_q = InValRdyQueueAdapter ( s.req )
s.resp_q = OutValRdyQueueAdapter ( s.resp )
# Concurrent block
@s.tick_fl
def block():
#-------------------------------------------------------------------
# TASK 3.2: Comment out the Exception below.
# Implement GcdUnitFL code shown on the slides.
#-------------------------------------------------------------------
raise NotImplementedError(
'GcdUnitMsg has not been implemented yet!\n '
'Put your implementation code here!'
)
def __init__( s ):
# Interface
s.req = InValRdyBundle ( GcdUnitReqMsg() )
s.resp = OutValRdyBundle ( Bits(16) )
# Adapters
s.req_q = InValRdyQueueAdapter ( s.req )
s.resp_q = OutValRdyQueueAdapter ( s.resp )
# Concurrent block
@s.tick_fl
def block():
# Use adapter to pop value from request queue
req_msg = s.req_q.popleft()
# Use gcd function from Python's standard library
result = gcd( req_msg.a, req_msg.b )
# Use adapter to append result to response queue
s.resp_q.append( result )
def __init__( s, mem_src_msgs, mem_sink_msgs, src_delay, sink_delay,
memreq_params, memresp_params ):
s.proc_go = InPort ( 1 )
s.proc_status = OutPort( 32 )
# Memory Request Port
s.memreq = OutValRdyBundle( memreq_params.nbits )
# Memory Respone Port
s.memresp = InValRdyBundle( memresp_params.nbits )
# Instantiate models
s.mem_src = TestSource( memreq_params.nbits, mem_src_msgs, src_delay )
s.mem_sink = TestSink ( memresp_params.nbits, mem_sink_msgs, sink_delay )
s.connect( s.mem_src.out, s.memreq )
s.connect( s.memresp, s.mem_sink.in_ )
@s.combinational
def comb():
s.proc_status.value = \
s.mem_src.done and s.mem_sink.done
def __init__(s,
cop_addr_nbits=5,
cop_data_nbits=32,
mem_addr_nbits=32,
mem_data_nbits=32):
# Config params
s.addr_nbits = cop_addr_nbits
s.data_nbits = cop_data_nbits
s.mreq_p = mem_msgs.MemReqParams(mem_addr_nbits, mem_data_nbits)
s.mresp_p = mem_msgs.MemRespParams(mem_data_nbits)
# COP interface
s.from_cpu = InValRdyBundle(s.addr_nbits + s.data_nbits)
s.to_cpu = OutMatrixVecBundle()
# Memory request/response ports
s.memreq = InValRdyBundle(s.mreq_p.nbits)
s.memresp = OutValRdyBundle(s.mresp_p.nbits)
# Internal functional model
s.mem = BytesMemPortProxy(s.mreq_p, s.mresp_p, s.memreq, s.memresp)
s.xcel_mvmult = MatrixVec(s.mem)
def __init__(s, nbits=8, mbits=1):
# Interface
s.req = InValRdyBundle(MapperReqMsg())
s.resp = OutValRdyBundle(MapperRespMsg())
# Instantiate datapath and control
s.dpath = MapperDpathRTL(nbits, mbits)
s.ctrl = MapperCtrlRTL(mbits)
# connect input interface to dpath/ctrl
s.connect(s.req.msg.data, s.dpath.req_msg_data)
s.connect(s.req.msg.type_, s.ctrl.req_msg_type)
s.connect(s.req.val, s.ctrl.req_val)
s.connect(s.resp.rdy, s.ctrl.resp_rdy)
# connect dpath/ctrl to output interface
s.connect(s.dpath.resp_msg_data, s.resp.msg.data)
s.connect(s.ctrl.resp_msg_type, s.resp.msg.type_)
s.connect(s.ctrl.req_rdy, s.req.rdy)
s.connect(s.ctrl.resp_val, s.resp.val)
# connect dpath/ctrl
s.connect(s.ctrl.result_reg_en, s.dpath.result_reg_en)
s.connect(s.ctrl.reference_reg_en, s.dpath.reference_reg_en)
def __init__(s, dtype, stages, pipeq, bypassq):
s.in_ = InValRdyBundle(dtype)
s.out = OutValRdyBundle(dtype)
s.in_q = InValRdyQueue(dtype, pipe=pipeq)
s.out_q = OutValRdyQueue(dtype, bypass=bypassq)
s.pipe = Pipeline(stages)
s.connect(s.in_, s.in_q.in_)
s.connect(s.out, s.out_q.out)
@s.tick
def logic():
# Automatically enq from input / deq from output
s.in_q.xtick()
s.out_q.xtick()
# No stall
if not s.out_q.is_full():
# Insert item into pipeline from input queue
if not s.in_q.is_empty():
s.pipe.insert(s.in_q.deq())
# Items graduating from pipeline, add to output queue
if s.pipe.ready():
s.out_q.enq(s.pipe.remove())
# Advance the pipeline
s.pipe.advance()
def __init__(s):
# Interface
s.req = InValRdyBundle(GcdUnitReqMsg())
s.resp = OutValRdyBundle(Bits(16))
# Instantiate datapath and control
s.dpath = GcdUnitDpathRTL()
s.ctrl = GcdUnitCtrlRTL()
# Connect input interface to dpath/ctrl
s.connect(s.req.msg.a, s.dpath.req_msg_a)
s.connect(s.req.msg.b, s.dpath.req_msg_b)
s.connect(s.req.val, s.ctrl.req_val)
s.connect(s.req.rdy, s.ctrl.req_rdy)
# Connect dpath/ctrl to output interface
s.connect(s.dpath.resp_msg, s.resp.msg)
s.connect(s.ctrl.resp_val, s.resp.val)
s.connect(s.ctrl.resp_rdy, s.resp.rdy)
# Connect status/control signals
s.connect_auto(s.dpath, s.ctrl)
def __init__(s, cpu_ifc_types):
s.cpu_ifc_req = InValRdyBundle(cpu_ifc_types.req)
s.cpu_ifc_resp = OutValRdyBundle(cpu_ifc_types.resp)
s.ss = InPort(StatusSignals())
s.cs = OutPort(CtrlSignals())
# Interface ports
s.in_val = Wire(1)
s.in_rdy = Wire(1)
s.out_val = Wire(1)
s.out_rdy = Wire(1)
# State element
s.STATE_IDLE = 0
s.STATE_LOAD = 1
s.STATE_CALC = 2
s.STATE_DONE = 3
s.state = regs.RegRst(2, reset_value=s.STATE_IDLE)
s.ctrl_msg = Wire(cpu_ifc_types.req.ctrl_msg)
def __init__(s, dtype):
s.in_ = InValRdyBundle(TRANSACTION_NBITS)
s.out = OutValRdyBundle(dtype)
# Static Elaboration
s.ctrl = IncrPipeCtrl()
s.dpath = IncrPipeDpath(dtype)
# s.connect ctrl
s.connect(s.ctrl.in_val, s.in_.val)
s.connect(s.ctrl.in_rdy, s.in_.rdy)
s.connect(s.ctrl.out_val, s.out.val)
s.connect(s.ctrl.out_rdy, s.out.rdy)
# s.connect dpath
s.connect(s.dpath.in_msg, s.in_.msg)
s.connect(s.dpath.out_msg, s.out.msg)
# s.connect ctrl signals (ctrl -> dpath )
s.connect(s.ctrl.a_reg_en, s.dpath.a_reg_en)
s.connect(s.ctrl.b_reg_en, s.dpath.b_reg_en)
s.connect(s.ctrl.c_reg_en, s.dpath.c_reg_en)
s.connect(s.ctrl.d_reg_en, s.dpath.d_reg_en)
s.connect(s.ctrl.e_reg_en, s.dpath.e_reg_en)
# s.connect status signals (ctrl <- dpath )
s.connect(s.ctrl.inst_b, s.dpath.inst_b)
def __init__(s, cpu_ifc_types):
s.cpu_ifc_req = InValRdyBundle(cpu_ifc_types.req)
s.cpu_ifc_resp = OutValRdyBundle(cpu_ifc_types.resp)
s.cpu_req_q = InValRdyQueue(cpu_ifc_types.req)
s.cpu_resp_q = OutValRdyQueue(cpu_ifc_types.resp)
def __init__(s, dtype, nmsgs):
s.nmsgs = nmsgs
# Queue interfaces
s.in_ = InValRdyBundle(dtype)
s.out = OutValRdyBundle(dtype)
# QueuePortProxy objects
s.in_queue = InQueuePortProxy(s.in_)
s.out_queue = OutQueuePortProxy(s.out)
# This looks like a regular tick block, but because it is a
# pausable_tick there is something more sophisticated is going on.
# The first time we call the tick, the queue_copy function will try
# and access the input queue. This will get proxied to the
# InQueuePortProxy object which will check the val/rdy interface. If
# the interface is not valid, we cannot return the data to the
# underlying queue_copy function so instead we use greenlets to
# switch back to the pausable tick function. The next time we call
# tick, we call the wrapper function again, and essentially we jump
# back into the InQueuePortProxy object to see if the interface is
# valid yet. When the interface is eventually valid, the
# InQueuePortProxy object will return the data and the underlying
# queue_copy function will move onto the next element. Currently the
# queue port proxy objects include infinite internal queues so the
# output queue can never stall.
@s.tick_fl
def logic():
queue_copy(s.nmsgs, s.in_queue, s.out_queue)
def __init__(s,
nlanes,
nmul_stages,
cop_addr_nbits=5,
cop_data_nbits=32,
mem_addr_nbits=32,
mem_data_nbits=32):
# Config Params
s.nlanes = nlanes
s.nmul_stages = nmul_stages
s.cop_addr_nbits = cop_addr_nbits
s.cop_data_nbits = cop_data_nbits
s.memreq_params = mem_msgs.MemReqParams(mem_addr_nbits, mem_data_nbits)
s.memresp_params = mem_msgs.MemRespParams(mem_data_nbits)
# Interface
s.from_cpu = InValRdyBundle(cop_addr_nbits + cop_data_nbits)
s.to_cpu = OutPort(1)
s.lane_req = [
OutValRdyBundle(s.memreq_params.nbits) for x in range(s.nlanes)
]
s.lane_resp = [
InValRdyBundle(s.memresp_params.nbits) for x in range(s.nlanes)
]
def __init__( s ):
#---------------------------------------------------------------------
# Interfaces
#---------------------------------------------------------------------
s.xcelreq = InValRdyBundle ( XcelReqMsg() )
s.xcelresp = OutValRdyBundle( XcelRespMsg() )
#---------------------------------------------------------------------
# Gcd XcelHLS
#---------------------------------------------------------------------
s.gcd_xcel = GcdXcelHLS()
s.connect( s.gcd_xcel.xcelreq.msg, s.xcelreq.msg )
#---------------------------------------------------------------------
# Send stage
#---------------------------------------------------------------------
# send the configuration message or the iterator message
s.do_send = Wire( 1 )
@s.combinational
def send_request():
s.gcd_xcel.xcelreq.val.value = ~s.pipe_stg.prev_stall & s.xcelreq.val
s.xcelreq.rdy.value = s.gcd_xcel.xcelreq.rdy & ~s.pipe_stg.prev_stall
s.do_send.value = s.xcelreq.val & s.xcelreq.rdy
#---------------------------------------------------------------------
# Receive stage
#---------------------------------------------------------------------
# receive response messages
s.pipe_stg = PipeCtrlFuture()
s.connect( s.pipe_stg.next_squash, 0 )
s.connect( s.pipe_stg.next_stall, 0 )
s.connect( s.pipe_stg.curr_squash, 0 )
s.connect( s.pipe_stg.prev_val, s.do_send )
s.xcelresp_q = SingleElementPipelinedQueue( XcelRespMsg() )
s.connect( s.gcd_xcel.xcelresp, s.xcelresp_q.enq )
s.connect( s.xcelresp_q.deq.msg, s.xcelresp.msg )
@s.combinational
def receive_response():
s.xcelresp_q.deq.rdy.value = s.pipe_stg.curr_val & s.xcelresp.rdy
s.xcelresp.val.value = s.pipe_stg.curr_val & s.xcelresp_q.deq.val
s.pipe_stg.curr_stall.value = \
s.pipe_stg.curr_val & ( ~s.xcelresp.rdy | ~s.xcelresp_q.deq.val )
def __init__( s, dtype ):
s.enq = InValRdyBundle ( dtype )
s.deq = OutValRdyBundle( dtype )
# Ctrl and Dpath unit instantiation
s.ctrl = SingleElementSkidQueueCtrl ()
s.dpath = SingleElementSkidQueueDpath( dtype )
# Ctrl unit connections
s.connect( s.ctrl.enq_val, s.enq.val )
s.connect( s.ctrl.enq_rdy, s.enq.rdy )
s.connect( s.ctrl.deq_val, s.deq.val )
s.connect( s.ctrl.deq_rdy, s.deq.rdy )
# Dpath unit connections
s.connect( s.dpath.enq_bits, s.enq.msg )
s.connect( s.dpath.deq_bits, s.deq.msg )
# Control Signal connections (ctrl -> dpath)
s.connect( s.dpath.wen, s.ctrl.wen )
s.connect( s.dpath.bypass_mux_sel, s.ctrl.bypass_mux_sel )
def __init__( s, num_entries, dtype ):
s.enq = InValRdyBundle ( dtype )
s.deq = OutValRdyBundle( dtype )
s.num_free_entries = OutPort( get_nbits(num_entries) )
# Ctrl and Dpath unit instantiation
s.ctrl = NormalQueueCtrl ( num_entries )
s.dpath = NormalQueueDpath( num_entries, dtype )
# Ctrl unit connections
s.connect( s.ctrl.enq_val, s.enq.val )
s.connect( s.ctrl.enq_rdy, s.enq.rdy )
s.connect( s.ctrl.deq_val, s.deq.val )
s.connect( s.ctrl.deq_rdy, s.deq.rdy )
s.connect( s.ctrl.num_free_entries, s.num_free_entries )
# Dpath unit connections
s.connect( s.dpath.enq_bits, s.enq.msg )
s.connect( s.dpath.deq_bits, s.deq.msg )
# Control Signal connections (ctrl -> dpath)
s.connect( s.dpath.wen, s.ctrl.wen )
s.connect( s.dpath.waddr, s.ctrl.waddr )
s.connect( s.dpath.raddr, s.ctrl.raddr )
def __init__(s, dtype):
s.in_ = InValRdyBundle(dtype)
s.out = OutValRdyBundle(dtype)
s.m = BundleExample(dtype)
s.connect(s.in_, s.m.req)
s.connect(s.out, s.m.resp)
def __init__(s):
# interface
s.in_control = InValRdyBundle(inst_msg()) # control word
s.memresp = InValRdyBundle(MemMsg(32, nWid).resp)
# 0,1: right/left neighbors
# 2,3: length-2 right/left PEs
# 4,5: length-4 right/left PEs
s.in_neighbor = InValRdyBundle[6](nWid)
s.memreq = OutValRdyBundle(MemMsg(32, nWid).req)
s.out_fsm = OutValRdyBundle(1) # response to FSM
s.out_neighbor = OutValRdyBundle[6](nWid)
# Queues
s.memreq_q = SingleElementBypassQueue(MemReqMsg(32, nWid))
s.connect(s.memreq, s.memreq_q.deq)
#s.memresp_q = SingleElementPipelinedQueue( MemRespMsg(16) )
s.memresp_q = SingleElementBypassQueue(MemRespMsg(nWid))
s.connect(s.memresp, s.memresp_q.enq)
# temporarily store destination for non-blocking loads
s.memdes_q = NormalQueue(nMemInst, nDesField)
# PE local register file
s.rf = RegisterFile(nWid, nReg, 2) # 2 read ports
# approx_mul
# input is done by reqMsg(src0, src1) done in control plane.
s.approx_mul = CombinationalApproxMult(nWid / 2, 4)
s.mul_msg = MymultReqMsg(nWid / 2)
# temporary variables
s.src0_tmp = Wire(nWid)
s.src1_tmp = Wire(nWid)
s.des_tmp = Wire(nWid)
s.go = Wire(1)
s.go_req = Wire(1)
s.go_resp = Wire(1)
s.go_mul = Wire(1)
s.reqsent = RegRst(1, 0)
def __init__(s, mapper_num=2, reducer_num=1):
# Interface
s.wcreq = InValRdyBundle(WordcountReqMsg())
s.wcresp = OutValRdyBundle(WordcountRespMsg())
s.memreq = OutValRdyBundle(MemReqMsg(8, 32, 32))
s.memresp = InValRdyBundle(MemRespMsg(8, 32))
# Framework Components
s.map = MapperPRTL[mapper_num]()
s.red = ReducerPRTL[reducer_num]()
s.sche = SchedulerPRTL()
# Connect Framework Components
for i in xrange(mapper_num):
s.connect_pairs(
s.sche.map_req[i],
s.map[i].req,
s.sche.map_resp[i],
s.map[i].resp,
)
for i in xrange(reducer_num):
s.connect_pairs(
s.sche.red_req[i],
s.red[i].req,
s.sche.red_resp[i],
s.red[i].resp,
)
s.connect_pairs(
s.sche.gmem_req,
s.memreq,
s.sche.gmem_resp,
s.memresp,
s.wcreq,
s.sche.in_,
s.wcresp,
s.sche.out,
)
