def test(test_params, dump_vcd): run_sim( TestHarness( MapperPRTL, test_params.msgs[::2], test_params.msgs[1::2], test_params.src_delay, test_params.sink_delay ), dump_vcd, )
def run_test(digitrec, test_params, dump_vcd, test_verilog=False): data = test_params.data ref = test_params.ref result = test_params.result data_bytes = struct.pack("<{}Q".format(len(data)), *data) digitrec_protocol_msgs = gen_protocol_msgs(len(data), ref, result) digitrec_reqs = digitrec_protocol_msgs[::2] digitrec_resps = digitrec_protocol_msgs[1::2] th = TestHarness( digitrec, digitrec_reqs, digitrec_resps, test_params.stall, test_params.latency, test_params.src_delay, test_params.sink_delay, dump_vcd, test_verilog, ) th.mem.write_mem(0x1000, data_bytes) run_sim(th, dump_vcd, max_cycles=500)
def run_test( pageRank, test_params, dump_vcd, test_verilog=False ): G_data = test_params.matrixG result = test_params.result R_data = test_params.vectorR runs = test_params.runs G_data_bytes = struct.pack("<{}L".format(len(G_data)), *G_data) R_data_bytes = struct.pack("<{}L".format(len(R_data)), *R_data) pageRank_protocol_msgs = gen_protocol_msgs( 8 , result, runs ) # len(data), result ) pageRank_reqs = pageRank_protocol_msgs[::2] pageRank_resps = pageRank_protocol_msgs[1::2] th = TestHarness( pageRank, pageRank_reqs, pageRank_resps, test_params.stall, test_params.latency, test_params.src_delay, test_params.sink_delay, dump_vcd, test_verilog ) th.mem.write_mem( 0x1000, G_data_bytes ) th.mem.write_mem( 0x2000, R_data_bytes ) run_sim( th, dump_vcd, max_cycles=MAX_CYCLES ) if ( runs == 1 ) : # Retrieve result from test memory result_bytes = struct.pack("<{}L".format(len(result_8data_1run)),*result_8data_1run ) result_bytes = th.mem.read_mem( 0x2000, len(result_bytes) ) result_list = list(struct.unpack("<{}L".format(len(result_8data_1run)), buffer(result_bytes))) if len(result_list) != len(result_8data_1run): print("FAIL, actual result has size " + str(len(result_list)) + " but should have " + str(len(result_8data_1run))) return noError = True for i in xrange(len(result_list)): if result_list[i] != result_8data_1run[i]: print("FAIL, actual result " + str(result_list[i]) + " but should have " + str(result_8data_1run[i])) noError = False if noError: print("PASS, Yay!") else : # Retrieve result from test memory result_bytes = struct.pack("<{}L".format(len(result_8data_4run)),*result_8data_4run ) result_bytes = th.mem.read_mem( 0x2000, len(result_bytes) ) result_list = list(struct.unpack("<{}L".format(len(result_8data_4run)), buffer(result_bytes))) if len(result_list) != len(result_8data_4run): print("FAIL, actual result has size " + str(len(result_list)) + " but should have " + str(len(result_8data_4run))) return noError = True for i in xrange(len(result_list)): if result_list[i] != result_8data_4run[i]: print("FAIL, actual result " + hex(result_list[i]) + " but should have " + hex(result_8data_4run[i])) noError = False if noError: print("PASS, Yay!")
def run_test( pageRank, test_params, dump_vcd, test_verilog=False ): data = test_params.data result = test_params.result data_bytes = struct.pack("<{}Q".format(len(data)), *data) pageRank_protocol_msgs = gen_protocol_msgs( len(data), result ) pageRank_reqs = pageRank_protocol_msgs[::2] pageRank_resps = pageRank_protocol_msgs[1::2] th = TestHarness( pageRank, pageRank_reqs, pageRank_resps, test_params.stall, test_params.latency, test_params.src_delay, test_params.sink_delay, dump_vcd, test_verilog ) th.mem.write_mem( 0x1000, data_bytes ) run_sim( th, dump_vcd, max_cycles=20 ) # Retrieve result from test memory result_bytes = struct.pack("<{}Q".format(len(test_8data)),*result_8data ) result_bytes = th.mem.read_mem( 0x2000, len(result_bytes) ) result_list = list(struct.unpack("<{}Q".format(len(result_8data)), buffer(result_bytes))) if len(result_list) != len(result_8data): print("FAIL, actual result has size " + str(len(result_list)) + " but should have " + str(len(result_8data))) return noError = True for i in xrange(len(result_list)): if result_list[i] != result_8data[i]: print("FAIL, actual result " + str(result_list[i]) + " but should have " + str(result_8data[i])) noError = False if noError: print("PASS, Yay!")
def test_2port(test_params, dump_vcd): msgs0 = test_params.msg_func(0x1000) msgs1 = test_params.msg_func(0x2000) run_sim( TestHarness(2, [msgs0[::2], msgs1[::2]], [msgs0[1::2], msgs1[1::2]], test_params.stall, test_params.lat, test_params.src, test_params.sink), dump_vcd)
def run_test( digitrec, test_params, dump_vcd, test_verilog=False ): data = test_params.data result = test_params.result data_bytes = struct.pack("<{}Q".format(len(data)), *data) digitrec_protocol_msgs = gen_protocol_msgs( len(data), result ) digitrec_reqs = digitrec_protocol_msgs[::2] digitrec_resps = digitrec_protocol_msgs[1::2] th = TestHarness( digitrec, digitrec_reqs, digitrec_resps, test_params.stall, test_params.latency, test_params.src_delay, test_params.sink_delay, dump_vcd, test_verilog ) th.mem.write_mem( 0x1000, data_bytes ) run_sim( th, dump_vcd, max_cycles=200000 ) # Retrieve result from test memory result_bytes = struct.pack("<{}Q".format(len(small_result_data)),*small_result_data ) result_bytes = th.mem.read_mem( 0x2000, len(result_bytes) ) result_list = list(struct.unpack("<{}Q".format(len(small_result_data)), buffer(result_bytes))) for i in xrange(len(result_list)): print(str(i) + "th data digit: " + str(result_list[i]) + " it shoud be " + str(small_result_data[i])) # Calculate error rate and print it accuracy = 0 for i in xrange(len(result_list)): if result_list[i] == small_result_data[i]: accuracy = accuracy + 1 error_rate = float((len(result_list)-accuracy))/len(result_list) print("Overall Error Rate is: " + str(error_rate*100) + "%")
def test_2port( test_params, dump_vcd ): msgs0 = test_params.msg_func(0x1000) msgs1 = test_params.msg_func(0x2000) run_sim( TestHarness( 2, [ msgs0[::2], msgs1[::2] ], [ msgs0[1::2], msgs1[1::2] ], test_params.stall, test_params.lat, test_params.src, test_params.sink ), dump_vcd )
def run_test( dut, test_params, dump_vcd = False, test_verilog = False, max_cycles=5000 ): # Setup the model testHarness = TestHarness(dut, test_verilog) # Run the simulation run_sim(testHarness, False, max_cycles = max_cycles)
def test_1port( test_params, dump_vcd ): msgs = test_params.msg_func(0x1000) for assoc in [1,2,4]: for ttset in [4,8,16]: run_sim( TestHarness( msgs[::2], msgs[1::2], test_params.stall, test_params.lat, test_params.src, test_params.sink, assoc, ttset), dump_vcd )
def run_test(reducer, test_params, dump_vcd, test_verilog=False): reducer_reqs = test_params.msgs[::2] reducer_resps = test_params.msgs[1::2] th = TestHarness(reducer, reducer_reqs, reducer_resps, test_params.src_delay, test_params.sink_delay, dump_vcd, test_verilog) run_sim(th, dump_vcd, max_cycles=70)
def run_test( reducer, test_params, dump_vcd, test_verilog=False ): reducer_reqs = test_params.msgs[::2] reducer_resps = test_params.msgs[1::2] th = TestHarness( reducer, reducer_reqs, reducer_resps, test_params.src_delay, test_params.sink_delay, dump_vcd, test_verilog ) run_sim( th, dump_vcd, max_cycles=70 )
def test_generic(): req_msgs = [ # src type opq addr len data req(0x0, 'gets', 0x00, 0x00000000, 0, 0), req(0x1, 'gets', 0x01, 0x00000000, 0, 0), req(0x1, 'gets', 0x02, 0x00000010, 0, 0), req(0x0, 'gets', 0x03, 0x00000010, 0, 0), req(0x0, 'getm', 0x04, 0x00000010, 0, 0), req(0x1, 'getm', 0x05, 0x00000010, 0, 0), req(0x0, 'gets', 0x06, 0x00000010, 0, 0), req(0x1, 'putm', 0x07, 0x00000010, 0, 0xbeefbeef), req(0x0, 'getm', 0x08, 0x00000010, 0, 0), ] resp_1_msgs = [ # type opq test len data resp('data', 0x00, 1, 0, 0xdeadbeef), resp('data', 0x03, 0, 0, 0x00c0ffee), resp('data', 0x04, 3, 0, 0x00c0ffee), resp('data', 0x08, 3, 0, 0xbeefbeef), ] resp_2_msgs = [ # type opq test len data resp('data', 0x01, 0, 0, 0xdeadbeef), resp('data', 0x02, 1, 0, 0x00c0ffee), resp('ack', 0x7, 0, 0, 0), ] fwd_1_msgs = [ req(0x2, 'fwdm', 0x05, 0x00000010, 0, 0), ] fwd_2_msgs = [ req(0x2, 'inv', 0x04, 0x00000010, 0, 0), req(0x2, 'fwds', 0x06, 0x00000010, 0, 0), req(0x2, 'inv', 0x08, 0x00000010, 0, 0), ] # Instantiate testharness harness = TestHarness(req_msgs, resp_1_msgs, resp_2_msgs, fwd_1_msgs, fwd_2_msgs, 0, 0, 0, 0, CoherentCacheFL, False, False) mem = [ # addr data (in int) 0x00000000, 0xdeadbeef, 0x00000010, 0x00c0ffee, ] # Load memory before the test harness.load(mem[::2], mem[1::2]) # Run the test run_sim(harness, False)
def test_dir_mapped(test_params, dump_vcd): msgs = test_params.msg_func(0) if test_params.mem_data_func != None: mem = test_params.mem_data_func(0) # Instantiate testharness harness = TestHarness(msgs[::2], msgs[1::2], test_params.stall, test_params.lat, test_params.src, test_params.sink, BlockingCacheFL, test_params.nbank, False, dump_vcd) # Load memory before the test if test_params.mem_data_func != None: harness.load(mem[::2], mem[1::2]) # Run the test run_sim(harness, dump_vcd)
def test_cachenet(test_params, dump_vcd): msgs = test_params.msg_func(0) if test_params.mem_data_func != None: mem = test_params.mem_data_func(0) # Instantiate testharness harness = TestHarness(msgs[::2], msgs[1::2], test_params.stall, test_params.lat, test_params.src, test_params.sink, dump_vcd) # Load memory before the test if test_params.mem_data_func != None: harness.load(mem[::2], mem[1::2]) # Run the test run_sim(harness, dump_vcd)
def test(test_params, dump_vcd, test_verilog): run_sim( TestHarness( GcdUnitRTL, test_params.msgs[::2], test_params.msgs[1::2], test_params.src_delay, test_params.sink_delay, dump_vcd, test_verilog, ), dump_vcd, )
def run_test(pageRank, test_params, dump_vcd, test_verilog=False): G_data = test_params.matrixG result = test_params.result R_data = test_params.vectorR runs = test_params.runs G_data_bytes = struct.pack("<{}L".format(len(G_data)), *G_data) R_data_bytes = struct.pack("<{}L".format(len(R_data)), *R_data) pageRank_protocol_msgs = gen_protocol_msgs(len(R_data), result, runs) # len(data), result ) pageRank_reqs = pageRank_protocol_msgs[::2] pageRank_resps = pageRank_protocol_msgs[1::2] th = TestHarness(pageRank, pageRank_reqs, pageRank_resps, test_params.stall, test_params.latency, test_params.src_delay, test_params.sink_delay, dump_vcd, test_verilog) th.mem.write_mem(0x1000, G_data_bytes) th.mem.write_mem(0x2000, R_data_bytes) run_sim(th, dump_vcd, max_cycles=MAX_CYCLES) # Retrieve result from test memory result_bytes = struct.pack("<{}L".format(len(result_8data_4run)), *result_8data_4run) result_bytes = th.mem.read_mem(0x2000, len(result_bytes)) result_list = list( struct.unpack("<{}L".format(len(result_8data_4run)), buffer(result_bytes))) if len(result_list) != len(result_8data_4run): print("FAIL, actual result has size " + str(len(result_list)) + " but should have " + str(len(result_8data_4run))) return noError = True for i in xrange(len(result_list)): if result_list[i] != result_8data_4run[i]: print("FAIL, actual result " + str(result_list[i]) + " but should have " + str(result_8data_4run[i])) noError = False if noError: print("PASS, Yay!")
def run_test( test_num, data_in_addr, data_in, data_out_addr, data_out ): # Convert test data into byte array data_in_bytes = struct.pack("<{}I".format(len(data_in)),*data_in) # Protocol messages msg = XcelReqMsg() msg.type_ = XcelReqMsg.TYPE_WRITE msg.raddr = 0 msg.data = test_num msg.opaque = 0xff xreqs = [ msg ] msg = XcelRespMsg() msg.type_ = XcelRespMsg.TYPE_WRITE msg.data = 0 msg.opaque = 0xff xresps = [ msg ] # Create test harness with protocol messagse th = TestHarness( MemStreamHLS(), xreqs, xresps ) # Load the data into the test memory th.mem.write_mem( data_in_addr, data_in_bytes ) # Run the test run_sim( th, dump_vcd=False, max_cycles=20000 ) # Retrieve data from test memory result_bytes = th.mem.read_mem( data_out_addr, len(data_out)*4 ) # Convert result bytes into list of ints result = list( struct.unpack( "<{}I".format(len(data_out)), buffer(result_bytes) )) # Compare result to sorted reference assert result == data_out
def run_test(test_num, data_in_addr, data_in, data_out_addr, data_out): # Convert test data into byte array data_in_bytes = struct.pack("<{}I".format(len(data_in)), *data_in) # Protocol messages msg = XcelReqMsg() msg.type_ = XcelReqMsg.TYPE_WRITE msg.raddr = 0 msg.data = test_num msg.opaque = 0x88 xreqs = [msg] msg = XcelRespMsg() msg.type_ = XcelRespMsg.TYPE_WRITE msg.data = 0 msg.opaque = 0x88 xresps = [msg] # Create test harness with protocol messagse th = TestHarness(MemProxyHLS(), xreqs, xresps) # Load the data into the test memory th.mem.write_mem(data_in_addr, data_in_bytes) # Run the test run_sim(th, dump_vcd=False, max_cycles=20000) # Retrieve data from test memory result_bytes = th.mem.read_mem(data_out_addr, len(data_out) * 4) # Convert result bytes into list of ints result = list( struct.unpack("<{}I".format(len(data_out)), buffer(result_bytes))) # Compare result to sorted reference assert result == data_out
def test_read_write_mem(dump_vcd): rgen = random.Random() rgen.seed(0x05a3e95b) # Test data we want to write into memory data = [rgen.randrange(-(2**31), 2**31) for _ in range(20)] # Convert test data into byte array data_bytes = struct.pack("<{}i".format(len(data)), *data) # Create memory messages to read and verify memory contents msgs = [] for i, item in enumerate(data): msgs.extend([ req('rd', 0x1, 0x1000 + 4 * i, 0, 0), resp('rd', 0x1, 0, item), ]) # Create test harness with above memory messages th = TestHarness(1, [msgs[::2]], [msgs[1::2]], 0, 0, 0, 0) # Write the data into the test memory th.mem.write_mem(0x1000, data_bytes) # Run the test run_sim(th, dump_vcd) # Read the data back out of the test memory result_bytes = th.mem.read_mem(0x1000, len(data_bytes)) # Convert result bytes into list of ints result = list(struct.unpack("<{}i".format(len(data)), result_bytes)) # Compare result to original data assert result == data
def run_test(digitrec, test_params, dump_vcd, test_verilog=False): data = test_params.data ref = test_params.ref result = test_params.result data_bytes = struct.pack("<{}Q".format(len(data)), *data) digitrec_protocol_msgs = gen_protocol_msgs(len(data), ref, result) digitrec_reqs = digitrec_protocol_msgs[::2] digitrec_resps = digitrec_protocol_msgs[1::2] th = TestHarness(digitrec, digitrec_reqs, digitrec_resps, test_params.stall, test_params.latency, test_params.src_delay, test_params.sink_delay, dump_vcd, test_verilog) th.mem.write_mem(0x1000, data_bytes) run_sim(th, dump_vcd, max_cycles=500)
def test_read_write_mem( dump_vcd ): rgen = random.Random() rgen.seed(0x05a3e95b) # Test data we want to write into memory data = [ rgen.randrange(-(2**31),2**31) for _ in range(20) ] # Convert test data into byte array data_bytes = struct.pack("<{}i".format(len(data)),*data) # Create memory messages to read and verify memory contents msgs = [] for i, item in enumerate(data): msgs.extend([ req( 'rd', 0x1000+4*i, 0, 0 ), resp( 'rd', 0, item ), ]) # Create test harness with above memory messages th = TestHarness( 1, [msgs[::2]], [msgs[1::2]], 0, 0, 0, 0 ) # Write the data into the test memory th.mem.write_mem( 0x1000, data_bytes ) # Run the test run_sim( th, dump_vcd ) # Read the data back out of the test memory result_bytes = th.mem.read_mem( 0x1000, len(data_bytes) ) # Convert result bytes into list of ints result = list(struct.unpack("<{}i".format(len(data)),result_bytes)) # Compare result to original data assert result == data
def run_test(xcel, test_params, dump_vcd, test_verilog=False): # Protocol messages xreqs = list() xresps = list() for i in xrange(len(test_params.msgs)): xcel_protocol_msgs = gen_xcel_protocol_msgs(test_params.msgs[i]) xreqs += xcel_protocol_msgs[::2] xresps += xcel_protocol_msgs[1::2] # Create test harness with protocol messagse th = TestHarness(xcel, xreqs, xresps, test_params.src, test_params.sink, dump_vcd, test_verilog) # Run the test run_sim(th, dump_vcd, max_cycles=20000)
def run_test( xcel, test_params, dump_vcd, test_verilog=False ): # Protocol messages xreqs = list() xresps = list() for i in xrange( len(test_params.msgs) ): xcel_protocol_msgs = gen_xcel_protocol_msgs( test_params.msgs[i] ) xreqs += xcel_protocol_msgs[::2] xresps += xcel_protocol_msgs[1::2] # Create test harness with protocol messagse th = TestHarness( xcel, xreqs, xresps, test_params.src, test_params.sink, dump_vcd, test_verilog ) # Run the test run_sim( th, dump_vcd, max_cycles=20000 )
def run_test( xcel, test_params, dump_vcd, test_verilog=False ): # Convert test data into byte array data = test_params.data data_bytes = struct.pack("<{}I".format(len(data)),*data) # Protocol messages xcel_protocol_msgs = gen_xcel_protocol_msgs( len(data) ) xreqs = xcel_protocol_msgs[::2] xresps = xcel_protocol_msgs[1::2] # Create test harness with protocol messagse th = TestHarness( xcel, xreqs, xresps, test_params.stall, test_params.lat, test_params.src, test_params.sink, dump_vcd, test_verilog ) # Load the data into the test memory th.mem.write_mem( 0x1000, data_bytes ) # Run the test run_sim( th, dump_vcd, max_cycles=20000 ) # Retrieve data from test memory result_bytes = th.mem.read_mem( 0x1000, len(data_bytes) ) # Convert result bytes into list of ints result = list(struct.unpack("<{}I".format(len(data)),buffer(result_bytes))) # Compare result to sorted reference assert result == sorted(data)
def run_test(xcel, test_params, dump_vcd, test_verilog=False): # Convert test data into byte array data = test_params.data data_bytes = struct.pack("<{}I".format(len(data)), *data) # Protocol messages xcel_protocol_msgs = gen_xcel_protocol_msgs(len(data)) xreqs = xcel_protocol_msgs[::2] xresps = xcel_protocol_msgs[1::2] # Create test harness with protocol messagse th = TestHarness(xcel, xreqs, xresps, test_params.stall, test_params.lat, test_params.src, test_params.sink, dump_vcd, test_verilog) # Load the data into the test memory th.mem.write_mem(0x1000, data_bytes) # Run the test run_sim(th, dump_vcd, max_cycles=20000) # Retrieve data from test memory result_bytes = th.mem.read_mem(0x1000, len(data_bytes)) # Convert result bytes into list of ints result = list(struct.unpack("<{}I".format(len(data)), buffer(result_bytes))) # Compare result to sorted reference assert result == sorted(data)
def run_test(digitrec, test_params, dump_vcd, test_verilog=False): data = test_params.data result = test_params.result data_bytes = struct.pack("<{}Q".format(len(data)), *data) digitrec_protocol_msgs = gen_protocol_msgs(len(data), result) digitrec_reqs = digitrec_protocol_msgs[::2] digitrec_resps = digitrec_protocol_msgs[1::2] th = TestHarness(digitrec, digitrec_reqs, digitrec_resps, test_params.stall, test_params.latency, test_params.src_delay, test_params.sink_delay, dump_vcd, test_verilog) th.mem.write_mem(0x1000, data_bytes) run_sim(th, dump_vcd, max_cycles=200000) # Retrieve result from test memory result_bytes = struct.pack("<{}Q".format(len(small_result_data)), *small_result_data) result_bytes = th.mem.read_mem(0x2000, len(result_bytes)) result_list = list( struct.unpack("<{}Q".format(len(small_result_data)), buffer(result_bytes))) for i in xrange(len(result_list)): print( str(i) + "th data digit: " + str(result_list[i]) + " it shoud be " + str(small_result_data[i])) # Calculate error rate and print it accuracy = 0 for i in xrange(len(result_list)): if result_list[i] == small_result_data[i]: accuracy = accuracy + 1 error_rate = float((len(result_list) - accuracy)) / len(result_list) print("Overall Error Rate is: " + str(error_rate * 100) + "%")
def test( test_params, dump_vcd ): run_sim( TestHarness( test_params.msgs, test_params.stall_prob, test_params.src_delay, test_params.sink_delay ), dump_vcd )
def test( test_params, dump_vcd, test_verilog ): run_sim( TestHarness( CombinationalApproxMult( nBits = 16, k=6 ), test_params.msgs[::2], test_params.msgs[1::2], test_params.src_delay, test_params.sink_delay, dump_vcd, test_verilog ) )
def test( test_params, dump_vcd, test_verilog ): run_sim( TestHarness( ApproxMult(nstages=2, nBits = 16, k=6 ), test_params.msgs[::2], test_params.msgs[1::2], test_params.src_delay, test_params.sink_delay, dump_vcd, test_verilog ) )
def test_1port(test_params, dump_vcd): msgs = test_params.msg_func(0x1000) run_sim( TestHarness(1, [msgs[::2]], [msgs[1::2]], test_params.stall, test_params.lat, test_params.src, test_params.sink), dump_vcd)
def test(test_params, dump_vcd): run_sim( TestHarness(test_params.msgs, test_params.nstages, test_params.src_delay, test_params.sink_delay), dump_vcd)
def test(test_params, dump_vcd, test_verilog): run_sim( TestHarness(GcdUnitRTL, test_params.msgs[::2], test_params.msgs[1::2], test_params.src_delay, test_params.sink_delay, dump_vcd, test_verilog), dump_vcd)
def test( test_params, dump_vcd ): run_sim( TestHarness( GcdUnitCL, test_params.msgs[::2], test_params.msgs[1::2], test_params.src_delay, test_params.sink_delay ), dump_vcd )
def test_1port( test_params, dump_vcd ): msgs = test_params.msg_func(0x1000) run_sim( TestHarness( 1, [ msgs[::2] ], [ msgs[1::2] ], test_params.stall, test_params.lat, test_params.src, test_params.sink ), dump_vcd )
def test( test_params, dump_vcd ): run_sim( TestHarness( IntMulFL(), test_params.msgs[::2], test_params.msgs[1::2], test_params.src_delay, test_params.sink_delay ), dump_vcd )
def test( test_params, dump_vcd, test_verilog ): run_sim( TestHarness( ApproxMultNStage( nstages=2, kBits=16 ), test_params.msgs[::2], test_params.msgs[1::2], test_params.src_delay, test_params.sink_delay, dump_vcd, test_verilog ) )
def test_128(dump_vcd, test_verilog): src_msgs, sink_msgs = gen_msgs(128) run_sim(TestHarness(128, src_msgs, sink_msgs, 0, 0, dump_vcd, test_verilog))
def test( test_params, dump_vcd, test_verilog ): run_sim( TestHarness( IntMulBaseRTL(), test_params.msgs[::2], test_params.msgs[1::2], test_params.src_delay, test_params.sink_delay, dump_vcd, test_verilog ), dump_vcd )
def test_64_delay( dump_vcd, test_verilog ): src_msgs, sink_msgs = gen_msgs( 64 ) run_sim( TestHarness( 64, src_msgs, sink_msgs, 3, 14, dump_vcd, test_verilog ) )
def test(test_params, dump_vcd): run_sim( TestHarness(MapperPRTL, test_params.msgs[::2], test_params.msgs[3::2], test_params.src_delay, test_params.sink_delay), dump_vcd)
def test( test_params, dump_vcd ): run_sim( TestHarness( FindMaxPRTL, test_params.msgs[::2], test_params.msgs[5::6], test_params.src_delay, test_params.sink_delay ), dump_vcd )
def test(test_params, dump_vcd, test_verilog): run_sim( TestHarness(CombinationalApproxMult(nBits=16, k=6), test_params.msgs[::2], test_params.msgs[1::2], test_params.src_delay, test_params.sink_delay, dump_vcd, test_verilog))
def test_coprime(test_params, dump_vcd): run_sim( TestHarness(GcdUnitFL, test_params.msgs[::2], test_params.msgs[1::2], test_params.src_delay, test_params.sink_delay), dump_vcd)
def test(test_params, dump_vcd, test_verilog): run_sim( TestHarness(IntMulAltRTL(), test_params.msgs[::2], test_params.msgs[1::2], test_params.src_delay, test_params.sink_delay, dump_vcd, test_verilog), dump_vcd)