Ejemplo n.º 1
0
import re

from periphondemand.bin.define import XMLEXT
from periphondemand.bin.define import DRIVERSPATH
from periphondemand.bin.define import COMPONENTSPATH
from periphondemand.bin.define import DRIVERS_TEMPLATES_PATH

from periphondemand.bin.utils.settings import Settings
from periphondemand.bin.utils.poderror import PodError
from periphondemand.bin.utils.wrapperxml import WrapperXml
from periphondemand.bin.utils import wrappersystem as sy
from periphondemand.bin.utils.display import Display

SETTINGS = Settings()
DISPLAY = Display()


class Driver(WrapperXml):
    """ Generate driver class """
    def __init__(self, project):
        self.project = project
        filepath = self.project.projectpath + "/" + \
            DRIVERSPATH + "/drivers" + XMLEXT
        if not sy.file_exist(filepath):
            raise PodError("No driver project found", 3)
        WrapperXml.__init__(self, file=filepath)
        self.bspdir = None

    def generate_project(self):
        """ copy template drivers files """
Ejemplo n.º 2
0
import time
import datetime

from periphondemand.bin.define import *
from periphondemand.bin.utils.settings import Settings
from periphondemand.bin.utils.error    import Error
from periphondemand.bin.utils.display  import Display
from periphondemand.bin.utils          import wrappersystem as sy

from periphondemand.bin.core.component  import Component
from periphondemand.bin.core.port       import Port
from periphondemand.bin.core.interface  import Interface
from periphondemand.bin.core.hdl_file   import Hdl_file

settings = Settings()
display = Display()
TAB = "    "

def generatepinout(self,filename=None):
    """ Generate the constraint file in tcl for quartus fpga
    """
    if filename is None:
        filename =  settings.projectpath+\
                    SYNTHESISPATH+"/"+ \
                    settings.active_project.getName()+"_pinout"+ TCLEXT
    self.project = settings.active_project
    out = "# Pinout file, automaticaly generated by pod\n"
    out = out + "package require ::quartus::project\n"

    for interface in self.project.getPlatform().getInterfacesList():
        for port in interface.getPortsList():