def saveInstance(self):
""" Save component in project directory files
"""
if not sy.dirExist(settings.projectpath + COMPONENTSPATH +"/"+ self.getInstanceName()):
sy.makeDirectory(settings.projectpath + COMPONENTSPATH +"/"+ self.getInstanceName())
self.saveXml(settings.projectpath + COMPONENTSPATH +"/" +\
self.getInstanceName() + "/" + self.getInstanceName() + ".xml")
def generateProject(self):
""" copy all hdl file in synthesis project directory
"""
for component in self.parent.getInstancesList():
if component.getNum() == "0":
# Make directory
compdir = settings.projectpath+SYNTHESISPATH+"/"+\
component.getName()
if sy.dirExist(compdir):
display.msg("Directory "+compdir+" exist, will be deleted")
sy.delDirectory(compdir)
sy.makeDirectory(compdir)
display.msg("Make directory for "+component.getName())
# copy hdl files
for hdlfile in component.getHdl_filesList():
try:
sy.copyFile(settings.projectpath+\
COMPONENTSPATH+\
"/"+\
component.getInstanceName()+\
"/hdl/"+\
hdlfile.getFileName(),
compdir+"/")
except IOError,e:
print display
raise Error(str(e),0)
def generateIntercon(masterinterface,intercon):
"""Generate intercon VHDL code for wishbone16 bus
"""
masterinstance = masterinterface.getParent()
syscon = masterinterface.getSysconInstance()
project = masterinstance.getParent()
###########################
#comment and header
VHDLcode = header(settings.author,intercon)
###########################
#entity
VHDLcode = VHDLcode + entity(intercon)
VHDLcode = VHDLcode + architectureHead(masterinterface,intercon)
###########################
#Clock and Reset connection
sysconinterface = syscon.getSysconInterface()
listslave = masterinterface.getSlavesList()
listinterfacesyscon = []
for slaveinstance in [slave.getInstance() for slave in listslave]:
listinterfacesyscon.append(slaveinstance.getSysconInterface())
listinterfacesyscon.append(masterinstance.getSysconInterface())
VHDLcode = VHDLcode + connectClockandReset(syscon,listinterfacesyscon)
###########################
#address decoding
VHDLcode = VHDLcode +\
addressdecoding(masterinterface,sysconinterface,intercon)
###########################
#controls slaves
VHDLcode = VHDLcode + controlslave(masterinterface,intercon)
###########################
#controls master
VHDLcode = VHDLcode+controlmaster(masterinterface,intercon)
###########################
#Foot
VHDLcode = VHDLcode + architectureFoot(intercon)
###########################
# saving
if not sy.dirExist(settings.projectpath +COMPONENTSPATH+"/"+\
intercon.getInstanceName()+"/"+HDLDIR):
sy.makeDirectory(settings.projectpath +COMPONENTSPATH+"/"+\
intercon.getInstanceName()+"/"+HDLDIR)
file = open(settings.projectpath +COMPONENTSPATH+"/"+\
intercon.getInstanceName()+"/"+HDLDIR+"/"+\
intercon.getInstanceName()+VHDLEXT,"w")
file.write(VHDLcode)
file.close()
#hdl file path
hdl = Hdl_file(intercon,
filename=intercon.getInstanceName()+\
VHDLEXT,istop=1,scope="both")
intercon.addHdl_file(hdl)
return VHDLcode
def setBSPDirectory(self,directory):
""" set the directory where drivers files must be copied """
lastdir = directory.split("/")[-1]
if lastdir != "POD":
raise Error("The directory must be named POD and not "+lastdir,0)
if sy.dirExist(directory):
if self.getNode(nodename="bsp") != None:
self.getNode(nodename="bsp").setAttribute("directory",directory)
else:
self.addNode(nodename="bsp",
attributename="directory",
value=directory)
self.bspdir = directory
else:
raise Error("Directory "+directory+" does not exist",0)
def generateProject(self):
""" copy template drivers files """
project = self.project
os = self.getName()
if os == None:
raise Error("Operating system must be selected",0)
for component in project.getInstancesList():
if component.getNum() == "0":
driverT = component.getDriver_Template(os)
if driverT != None:
if sy.dirExist(settings.projectpath+DRIVERSPATH+"/"+component.getName()):
display.msg("Driver directory for "+component.getName()+\
" allready exist. suppressing it")
sy.delDirectory(settings.projectpath+DRIVERSPATH+"/"+component.getName())
display.msg("Create directory for "+component.getName()+" driver")
# create component directory
sy.makeDirectory(settings.projectpath+DRIVERSPATH+"/"+component.getName())
else:
display.msg("No driver for "+component.getName())
def generateIntercon(masterinterface, intercon):
"""Generate intercon VHDL code for wishbone16 bus
"""
masterinstance = masterinterface.getParent()
project = masterinstance.getParent()
###########################
#comment and header
VHDLcode = header(settings.author,intercon)
###########################
#entity
VHDLcode = VHDLcode + entity(intercon)
VHDLcode = VHDLcode + architectureHead(masterinterface, intercon)
###########################
#Clock and Reset connection
VHDLcode = VHDLcode + connectClockandReset(masterinterface,intercon)
#Foot
VHDLcode = VHDLcode + architectureFoot(intercon)
###########################
# saving
if not sy.dirExist(settings.projectpath +
COMPONENTSPATH+"/"+
intercon.getInstanceName()+"/"+HDLDIR):
sy.makeDirectory(settings.projectpath+
COMPONENTSPATH+"/"+
intercon.getInstanceName()+"/"+HDLDIR)
file = open(settings.projectpath +COMPONENTSPATH+"/"+
intercon.getInstanceName()+
"/"+HDLDIR+"/"+intercon.getInstanceName()+VHDLEXT,"w")
file.write(VHDLcode)
file.close()
#hdl file path
hdl = Hdl_file(intercon,
filename=intercon.getInstanceName()+VHDLEXT,
istop=1,scope="both")
intercon.addHdl_file(hdl)
return VHDLcode
def createComponent(self,componentname,libraryname,versionname):
""" Creating new component 'componentname' for
library 'libraryname'
"""
librarypath = settings.active_library.getLibraryPath(libraryname)
componentpath = os.path.join(librarypath,componentname)
# verify if component and version exist
if sy.fileExist(os.path.join(componentpath,versionname+XMLEXT)):
settings.active_component = None
raise Error("Component version "+componentname+"."+versionname+\
" already exist")
# make directories if component is really new
if not sy.dirExist(componentpath):
sy.makeDirectory(componentpath)
sy.makeDirectory(os.path.join(componentpath,"hdl"))
sy.makeDirectory(os.path.join(componentpath,"doc"))
sy.makeDirectory(os.path.join(componentpath,"drivers_templates"))
# create xml file
WrapperXml.__init__(self,nodename="component")
self.setName(componentname)
self.saveComponent(os.path.join(componentpath,versionname))
self.setVersionName(versionname)
"""\
Usage : create <projectname>
create new project
"""
try:
self.checkargs(line,"<projectname>")
except Error,e:
print e
return
try:
sy.check_name(line)
except Error,e:
print e
return 0
dirname = os.path.abspath(line)
if sy.dirExist(dirname):
print "Project "+line+" already exists"
return 0
else:
try:
settings.active_project = Project(dirname,void=0)
except Error,e:
print e
return
self.setPrompt("POD",settings.active_project.getName())
print "Project "+settings.active_project.getName()+" created"
def complete_load(self,text,line,begidx,endidx):
""" complete load command with files under directory """
path = line.split(" ")[1]
