def test_all_candidate_instructions_are_offered_to_the_destinaton_unit(
self):
"""Test candidate instructions aren't shortlisted.
`self` is this test case.
"""
in_unit, out_unit = (UnitModel(ICaseString(name), width,
["ALU", "MEM"],
LockInfo(rd_lock, wr_lock), mem_acl)
for name, width, rd_lock, wr_lock, mem_acl in [(
"input", 3, True, False,
[]), ("output", 2, False, True, ["MEM"])])
proc_desc = ProcessorDesc([in_unit], [FuncUnit(out_unit, [in_unit])],
[], [])
self.assertEqual(
simulate([
HwInstruction([], *instr_params) for instr_params in
[["R1", "MEM"], ["R2", "MEM"], ["R3", "ALU"]]
], HwSpec(proc_desc)), [
BagValDict(cp_util) for cp_util in [{
ICaseString("input"):
map(InstrState, [0, 1, 2])
}, {
ICaseString("output"):
map(InstrState, [0, 2]),
ICaseString("input"):
[InstrState(1, StallState.STRUCTURAL)]
}, {
ICaseString("output"): [InstrState(1)]
}]
])
def test_capability_case_is_checked_across_all_units(self, caplog, unit):
"""Test ACL capability cases are checked across all units.
`self` is this test case.
`caplog` is the log capture fixture.
"""
caplog.set_level(WARNING)
in_out_units = (UnitModel(ICaseString(name), 1, [ICaseString("ALU")],
LockInfo(True, True),
map(ICaseString, capabilities))
for name, capabilities in [(unit,
[]), ("core 2", ["ALU"])])
assert load_proc_desc({
"units": [{
UNIT_NAME_KEY: unit,
UNIT_WIDTH_KEY: 1,
UNIT_CAPS_KEY: ["ALU"],
**{attr: True
for attr in [UNIT_RLOCK_KEY, UNIT_WLOCK_KEY]}
}, {
UNIT_NAME_KEY: "core 2",
UNIT_WIDTH_KEY: 1,
UNIT_CAPS_KEY: ["ALU"],
**{attr: True
for attr in [UNIT_RLOCK_KEY, UNIT_WLOCK_KEY]}, UNIT_MEM_KEY:
["alu"]
}],
"dataPath": []
}) == ProcessorDesc([], [], in_out_units, [])
assert caplog.records
warn_msg = caplog.records[0].getMessage()
for token in ["alu", "core 2", "ALU", unit]:
assert token in warn_msg
def test_capability_with_nonstandard_case_is_detected(
self, caplog, unit, acl_cap):
"""Test loading an ACL with a non-standard capability case.
`self` is this test case.
`caplog` is the log capture fixture.
`unit` is the loaded unit name.
`acl_cap` is the ACL capability to verify.
"""
caplog.set_level(WARNING)
ref_cap = acl_cap.upper()
assert load_proc_desc({
"units": [{
UNIT_NAME_KEY: unit,
UNIT_WIDTH_KEY: 1,
UNIT_CAPS_KEY: [ref_cap],
**{attr: True
for attr in [UNIT_RLOCK_KEY, UNIT_WLOCK_KEY]}, UNIT_MEM_KEY:
[acl_cap]
}],
"dataPath": []
}) == ProcessorDesc([], [], [
UnitModel(ICaseString(unit), 1, [ICaseString(ref_cap)],
LockInfo(True, True), [ICaseString(ref_cap)])
], [])
assert caplog.records
warn_msg = caplog.records[0].getMessage()
for token in [acl_cap, unit, ref_cap]:
assert token in warn_msg
def test_write_registers_are_not_checked_in_units_without_write_lock(self):
"""Test opportune write register access check.
`self` is this test case.
"""
in_unit, out_unit = (UnitModel(
ICaseString(name), 1, ["ALU"], LockInfo(rd_lock, wr_lock),
[]) for name, rd_lock, wr_lock in [("input", False,
False), ("output", True,
True)])
proc_desc = ProcessorDesc([in_unit], [FuncUnit(out_unit, [in_unit])],
[], [])
self.assertEqual(
simulate([
HwInstruction(*instr_regs, "ALU")
for instr_regs in [[["R1"], "R2"], [[], "R1"]]
], HwSpec(proc_desc)), [
BagValDict(cp_util) for cp_util in [{
ICaseString("input"): [InstrState(0)]
}, {
ICaseString("input"): [InstrState(1)],
ICaseString("output"): [InstrState(0)]
}, {
ICaseString("output"): [InstrState(1)]
}]
])
def test_RLock_in_unit_before_WLock(self):
"""Test detecting RAW hazards with read locks in earlier units.
`self` is this test case.
"""
in_unit, mid, out_unit = (UnitModel(ICaseString(name), 1, ["ALU"],
LockInfo(rd_lock, wr_lock), [])
for name, rd_lock, wr_lock in [(
"input", False,
False), ("middle", True,
False), ("output", False,
True)])
proc_desc = ProcessorDesc([in_unit], [FuncUnit(out_unit, [mid])], [],
[FuncUnit(mid, [in_unit])])
self.assertEqual(
simulate([
HwInstruction(*instr_regs, "ALU")
for instr_regs in [[[], "R1"], [["R1"], "R2"]]
], HwSpec(proc_desc)), [
BagValDict(cp_util) for cp_util in [{
ICaseString("input"): [InstrState(0)]
}, {
ICaseString("input"): [InstrState(1)],
ICaseString("middle"): [InstrState(0)]
}, {
ICaseString("middle"): [InstrState(1, StallState.DATA)],
ICaseString("output"): [InstrState(0)]
}, {
ICaseString("middle"): [InstrState(1)]
}, {
ICaseString("output"): [InstrState(1)]
}]
])
def test_instructions_flow_seamlessly(self):
"""Test instructions are moved successfully along the pipeline.
`self` is this test case.
"""
big_input, small_input1, mid1, small_input2, mid2, out_unit = (
UnitModel(ICaseString(name), width, ["ALU"], LockInfo(
rd_lock, wr_lock), []) for name, width, rd_lock, wr_lock in
[("big input", 4, True, False), ("small input 1", 1, True, False),
("middle 1", 1, False, False), ("small input 2", 1, True, False),
("middle 2", 2, False, False), ("output", 2, False, True)])
proc_desc = ProcessorDesc([big_input, small_input1, small_input2], [
FuncUnit(out_unit, [big_input, mid2])], [], starmap(FuncUnit, [
[mid2, [mid1, small_input2]], [mid1, [small_input1]]]))
self.assertEqual(simulate(
[HwInstruction([], out_reg, "ALU") for out_reg in
["R1", "R2", "R3", "R4", "R5", "R6"]],
HwSpec(proc_desc)), [BagValDict(cp_util) for cp_util in [
{ICaseString("big input"): map(InstrState, [0, 1, 2, 3]),
ICaseString("small input 1"): [InstrState(4)],
ICaseString("small input 2"): [InstrState(5)]},
{ICaseString("big input"): (InstrState(
instr, StallState.STRUCTURAL) for instr in [2, 3]),
ICaseString("output"): map(InstrState, [0, 1]),
ICaseString("middle 1"): [InstrState(4)],
ICaseString("middle 2"): [InstrState(5)]},
{ICaseString("output"): map(InstrState, [2, 3]),
ICaseString("middle 2"):
starmap(InstrState, [[5, StallState.STRUCTURAL], [4]])},
{ICaseString("output"): map(InstrState, [4, 5])}]])
def test_hazard(self):
"""Test structural hazards in a unified memory architecture.
`self` is this test case.
"""
in_unit, out_unit = (UnitModel(
ICaseString(name), 1, ["ALU", "MEM"], LockInfo(rd_lock, wr_lock),
mem_acl) for name, rd_lock, wr_lock, mem_acl in [(
"input", True, False,
["ALU", "MEM"]), ("output", False, True, ["MEM"])])
proc_desc = ProcessorDesc([in_unit], [FuncUnit(out_unit, [in_unit])],
[], [])
self.assertEqual(
simulate([
HwInstruction([], out_reg, "ALU") for out_reg in ["R1", "R2"]
], HwSpec(proc_desc)), [
BagValDict(cp_util) for cp_util in [{
ICaseString("input"): [InstrState(0)]
}, {
ICaseString("output"): [InstrState(0)],
ICaseString("input"): [InstrState(1)]
}, {
ICaseString("output"): [InstrState(1)]
}]
])
def chk_two_units(proc_dir, proc_file):
"""Verify a two-unit processor.
`proc_dir` is the directory containing the processor description file.
`proc_file` is the processor description file.
The function asserts the order and descriptions of units and links
among them.
"""
proc_desc = read_proc_file(proc_dir, proc_file)
alu_cap = ICaseString("ALU")
out_unit = ICaseString("output")
assert proc_desc == processor_utils.ProcessorDesc(
[UnitModel(
ICaseString("input"), 1, [alu_cap], LockInfo(True, False), [])],
[processor_utils.units.FuncUnit(UnitModel(out_unit, 1, [
alu_cap], LockInfo(False, True), []), proc_desc.in_ports)], [], [])
def test_instructions_are_loaded_to_lexicographically_inputs_first(self):
"""Test instructions are fed into sorted input units.
`self` is this test case.
"""
in_unit, out_unit = (UnitModel(ICaseString(name), 1, ["ALU"], LockInfo(
rd_lock, wr_lock), mem_acl) for name, rd_lock, wr_lock, mem_acl in
[("input 1", True, False, []),
("output 1", False, True, ["ALU"])])
proc_desc = ProcessorDesc(
[in_unit], [FuncUnit(out_unit, [in_unit])], [UnitModel(ICaseString(
"input 2"), 1, ["ALU"], LockInfo(True, False), [])], [])
self.assertEqual(simulate(
[HwInstruction([], "R1", "ALU")], HwSpec(proc_desc)), [BagValDict(
cp_util) for cp_util in [{ICaseString("input 1"): [InstrState(
0)]}, {ICaseString("output 1"): [InstrState(0)]}]])
def _chk_one_unit(proc_dir, proc_file):
"""Verify a single unit processor.
`proc_dir` is the directory containing the processor description file.
`proc_file` is the processor description file.
"""
assert read_proc_file(proc_dir, proc_file) == ProcessorDesc([], [], [
UnitModel(ICaseString("full system"), 1, [ICaseString("ALU")],
LockInfo(True, True), [])
], [])
def test_earlier_instructions_are_propagated_first(self):
"""Test earlier instructions are selected first.
`self` is this test case.
"""
in_units = [UnitModel(
ICaseString(name), 1, [categ], LockInfo(True, False), []) for name,
categ in [("ALU input", "ALU"), ("MEM input", "MEM")]]
out_unit = UnitModel(ICaseString("output"), 1, ["ALU", "MEM"],
LockInfo(False, True), [])
proc_desc = ProcessorDesc(
in_units, [FuncUnit(out_unit, in_units)], [], [])
self.assertEqual(simulate([HwInstruction(
*instr_params) for instr_params in [[[], "R12", "MEM"], [
["R11", "R15"], "R14", "ALU"]]], HwSpec(proc_desc)), [
BagValDict(inst_util) for inst_util in
[{ICaseString("MEM input"): [InstrState(0)],
ICaseString("ALU input"): [InstrState(1)]},
{ICaseString("output"): [InstrState(0)], ICaseString(
"ALU input"): [InstrState(1, StallState.STRUCTURAL)]},
{ICaseString("output"): [InstrState(1)]}]])
def test_hazard(self, in_width, in_mem_util, out_unit_params, extra_util):
"""Test detecting structural hazards.
`self` is this test case.
`in_width` is the width of the input unit.
`in_mem_util` is the list of input unit capabilities requiring
memory utilization.
`out_unit_params` are the creation parameters of output units.
`extra_util` is the extra utilization beyond the second clock
pulse.
"""
in_unit = UnitModel(ICaseString("input"), in_width, ["ALU"],
LockInfo(True, False), in_mem_util)
out_units = (UnitModel(ICaseString(name), width, ["ALU"],
LockInfo(False, True), mem_access)
for name, width, mem_access in out_unit_params)
out_units = (FuncUnit(out_unit, [in_unit]) for out_unit in out_units)
cp1_util = {ICaseString("input"): map(InstrState, range(in_width))}
assert simulate(
[HwInstruction([], out_reg, "ALU") for out_reg in ["R1", "R2"]],
HwSpec(ProcessorDesc([in_unit], out_units, [], []))) == list(
map(BagValDict, more_itertools.prepend(cp1_util, extra_util)))
def test_processor_with_four_connected_functional_units(self):
"""Test loading a processor with four functional units.
`self` is this test case.
"""
proc_desc = read_proc_file("processors",
"4ConnectedUnitsProcessor.yaml")
alu_cap = ICaseString("ALU")
wr_lock = LockInfo(False, True)
out_ports = tuple(
FuncUnit(UnitModel(name, 1, [alu_cap], wr_lock, []), predecessors)
for name, predecessors in [(ICaseString("output 1"),
proc_desc.in_ports),
(ICaseString("output 2"),
(unit.model
for unit in proc_desc.internal_units
))])
in_unit = ICaseString("input")
internal_unit = UnitModel(ICaseString("middle"), 1, [alu_cap],
LockInfo(False, False), [])
assert proc_desc == ProcessorDesc(
[UnitModel(in_unit, 1, [alu_cap], LockInfo(True, False), [])],
out_ports, [], [FuncUnit(internal_unit, proc_desc.in_ports)])
def test_mem_util_in_earlier_inputs_affects_later_ones(self):
"""Test propagation of memory utilization among inputs.
`self` is this test case.
"""
full_sys_unit = UnitModel(ICaseString("full system"), 2, ["ALU"],
LockInfo(True, True), ["ALU"])
res_util = (BagValDict(
{ICaseString("full system"): [InstrState(instr)]})
for instr in [0, 1])
assert simulate(
[HwInstruction([], out_reg, "ALU") for out_reg in ["R1", "R2"]],
HwSpec(ProcessorDesc([], [], [full_sys_unit],
[]))) == list(res_util)
def test_hazard(self):
"""Test detecting RAR hazards.
`self` is this test case.
"""
proc_desc = ProcessorDesc([], [], [
UnitModel(ICaseString(TEST_DIR), 2, ["ALU"], LockInfo(True, True),
[])
], [])
self.assertEqual(
simulate([
HwInstruction(["R1"], out_reg, "ALU")
for out_reg in ["R2", "R3"]
], HwSpec(proc_desc)),
[BagValDict({ICaseString(TEST_DIR): map(InstrState, [0, 1])})])
def test_same_capability_with_different_cases_in_two_units_is_detected(
self, caplog):
"""Test loading a capability with different cases in two units.
`self` is this test case.
`caplog` is the log capture fixture.
"""
caplog.set_level(WARNING)
in_file = "twoCapabilitiesWithSameNameAndDifferentCaseInTwoUnits.yaml"
processor = (UnitModel(ICaseString(unit_name), 1, [ICaseString("ALU")],
LockInfo(True, True), [])
for unit_name in ["core 1", "core 2"])
assert read_proc_file("capabilities",
in_file) == ProcessorDesc([], [], processor, [])
chk_warn(["ALU", "core 1", "alu", "core 2"], caplog.records)
assert ICaseString.__name__ not in caplog.records[0].getMessage()
def test_hazard(self, instr_regs):
"""Test detecting data hazards.
`self` is this test case.
`instr_regs` are the registers accessed by each instruction.
"""
full_sys_unit = UnitModel(ICaseString(TEST_DIR), 2, ["ALU"],
LockInfo(True, True), [])
assert simulate(
[HwInstruction(*regs, "ALU") for regs in instr_regs],
HwSpec(ProcessorDesc([], [], [full_sys_unit], []))) == [
BagValDict(cp_util) for cp_util in [{
ICaseString(TEST_DIR):
itertools.starmap(InstrState, [[0], [1, StallState.DATA]])
}, {
ICaseString(TEST_DIR): [InstrState(1)]
}]
]
def test_processor_with_explicit_attributes(self):
"""Test loading a processor with explicitly defined attributes.
`self` is this test case.
"""
assert load_proc_desc({
"units": [{
UNIT_NAME_KEY: "full system",
UNIT_WIDTH_KEY: 1,
UNIT_CAPS_KEY: ["ALU"],
**{attr: True
for attr in [UNIT_RLOCK_KEY, UNIT_WLOCK_KEY]}, UNIT_MEM_KEY:
["ALU"]
}],
"dataPath": []
}) == ProcessorDesc([], [], [
UnitModel(ICaseString("full system"), 1, [ICaseString("ALU")],
LockInfo(True, True), [ICaseString("ALU")])
], [])
def test_partial_mem_access(self):
"""Test loading a processor with partial memory access.
`self` is this test case.
"""
assert load_proc_desc({
"units": [{
UNIT_NAME_KEY: "full system",
UNIT_WIDTH_KEY: 1,
UNIT_CAPS_KEY: ["ALU", "MEM"],
**{attr: True
for attr in [UNIT_RLOCK_KEY, UNIT_WLOCK_KEY]}, UNIT_MEM_KEY:
["MEM"]
}],
"dataPath": []
}) == ProcessorDesc([], [], [
UnitModel(ICaseString("full system"), 1,
map(ICaseString, ["ALU", "MEM"]), LockInfo(True, True),
[ICaseString("MEM")])
], [])
def test_internal_stall_is_detected(self):
"""Test detecting stalls in internal units.
`self` is this test case.
"""
in_unit, mid, out_unit = (
UnitModel(ICaseString(name), width, ["ALU"],
LockInfo(rd_lock, wr_lock), []) for
name, width, rd_lock, wr_lock in [("input", 2, True, False), (
"middle", 2, False, False), ("output", 1, False, True)])
proc_desc = ProcessorDesc([in_unit], [FuncUnit(out_unit, [mid])], [],
[FuncUnit(mid, [in_unit])])
self.assertEqual(simulate(
[HwInstruction([], out_reg, "ALU") for out_reg in ["R1", "R2"]],
HwSpec(proc_desc)), [BagValDict(cp_util) for cp_util in [
{ICaseString("input"): map(InstrState, [0, 1])},
{ICaseString("middle"): map(InstrState, [0, 1])},
{ICaseString("middle"): [InstrState(1, StallState.STRUCTURAL)],
ICaseString("output"): [InstrState(0)]},
{ICaseString("output"): [InstrState(1)]}]])
def test_only_mem_access_instructions_are_checked(self):
"""Test always allowing instructions without memory access.
`self` is this test case.
"""
in_unit, out_unit = (UnitModel(ICaseString(name), 2, ["ALU", "MEM"],
LockInfo(rd_lock, wr_lock), mem_acl)
for name, rd_lock, wr_lock, mem_acl in [(
"input", True, False,
[]), ("output", False, True, ["MEM"])])
proc_desc = ProcessorDesc([in_unit], [FuncUnit(out_unit, [in_unit])],
[], [])
self.assertEqual(
simulate([
HwInstruction([], *instr_params)
for instr_params in [["R1", "MEM"], ["R2", "ALU"]]
], HwSpec(proc_desc)), [
BagValDict({ICaseString(unit): map(InstrState, [0, 1])})
for unit in ["input", "output"]
])
def test_stalled_outputs_are_not_flushed(self, extra_instr_lst):
"""Test data hazards at output ports.
`self` is this test case.
`extra_instr_lst` is the extra instructions to execute after the
ones causing the hazard.
"""
program = starmap(HwInstruction, chain(
[[[], "R1", "ALU"], [["R1"], "R2", "ALU"]], extra_instr_lst))
extra_instr_len = len(extra_instr_lst)
cores = starmap(lambda name, width: UnitModel(
ICaseString(name), width, ["ALU"], LockInfo(True, True), []),
[("core 1", 1), ("core 2", 1 + extra_instr_len)])
extra_instr_seq = range(2, 2 + extra_instr_len)
assert simulate(
tuple(program), HwSpec(ProcessorDesc([], [], cores, []))) == [
BagValDict(cp_util) for cp_util in
[{ICaseString("core 1"): [InstrState(0)], ICaseString(
"core 2"): starmap(InstrState, more_itertools.prepend(
[1, StallState.DATA],
([instr] for instr in extra_instr_seq)))},
{ICaseString("core 2"): [InstrState(1)]}]]
def test_util_tbl_exists_in_StallError(self):
"""Test dumping the utilizaiton table in stall errors.
`self` is this test case.
"""
long_input, mid, short_input, out_unit = (
UnitModel(ICaseString(name), 1, ["ALU"],
LockInfo(rd_lock, wr_lock), []) for name, rd_lock,
wr_lock in [("long input", False, False), ("middle", False, False),
("short input", False, False), ("output", True, True)])
proc_desc = ProcessorDesc([long_input, short_input], [FuncUnit(
out_unit, [mid, short_input])], [], [FuncUnit(mid, [long_input])])
with self.assertRaises(StallError) as ex_chk:
simulate([HwInstruction(*instr_regs, "ALU") for instr_regs in
[[[], "R1"], [["R1"], "R2"]]], HwSpec(proc_desc))
self.assertEqual(ex_chk.exception.processor_state, [
BagValDict(cp_util) for cp_util in
[{ICaseString("long input"): [InstrState(0)], ICaseString(
"short input"): [InstrState(1)]},
{ICaseString("middle"): [InstrState(0)], ICaseString("output"):
[InstrState(1, StallState.DATA)]},
{ICaseString("middle"): [InstrState(0, StallState.STRUCTURAL)],
ICaseString("output"): [InstrState(1, StallState.DATA)]}]])
def test_processor_puts_units_in_post_order(self):
"""Test putting units in post-order.
`self` is this test case.
"""
in_unit, mid1_unit, mid2_unit, mid3_unit, out_unit = (UnitModel(
ICaseString(name), 1, ["ALU"], LockInfo(rd_lock, wr_lock),
[]) for name, rd_lock, wr_lock in [(
"input", True,
False), ("middle 1", False,
False), ("middle 2", False,
False), ("middle 3", False,
False), ("output", False, True)])
assert ProcessorDesc(
[in_unit], [FuncUnit(out_unit, [mid3_unit])], [],
(FuncUnit(model, [pred])
for model, pred in [(mid1_unit, in_unit), (
mid3_unit, mid2_unit), (
mid2_unit, mid1_unit)])).internal_units == tuple(
FuncUnit(model, [pred]) for model, pred in [(
mid3_unit,
mid2_unit), (mid2_unit,
mid1_unit), (mid1_unit, in_unit)])
