def test_write_long(la: LogicAnalyzer, slave: I2CSlave):
la.capture(2, block=False)
slave.write_long(WRITE_DATA, REGISTER_ADDRESS)
la.stop()
scl, sda = la.fetch_data()
assert len(scl) == (SCL_START + SCL_WRITE * 6 + SCL_STOP)
assert len(sda) == (SDA_START + SDA_DEVICE_ADDRESS + SDA_REGISTER_ADDRESS +
SDA_WRITE * 4 + SDA_ACK)
def test_write(la: LogicAnalyzer, slave: I2CSlave):
la.capture(2, block=False)
slave.write(bytearray(b"\x00"), REGISTER_ADDRESS)
la.stop()
scl, sda = la.fetch_data()
assert len(scl) == (SCL_START + SCL_WRITE * 3 + SCL_STOP)
assert len(sda) == (SDA_START + SDA_DEVICE_ADDRESS + SDA_REGISTER_ADDRESS +
SDA_WRITE + SDA_ACK)
def test_stop_slave(la: LogicAnalyzer, slave: I2CSlave):
slave._start(1)
la.capture(2, block=False)
slave._stop()
la.stop()
init = la.get_initial_states()
scl, sda = la.fetch_data()
assert not init[SCL] and init[SDA] # SDA starts HIGH, SCL starts LOW.
assert sda[0] < scl[0] < sda[1] # Stop bit: SDA 0->1 while SCL is 1.
def test_start_slave(la: LogicAnalyzer, slave: I2CSlave):
la.capture(2, block=False)
slave._start(1)
la.stop()
slave._stop()
init = la.get_initial_states()
scl, sda = la.fetch_data()
assert all([init[c] for c in [SCL, SDA]]) # Both start HIGH.
assert sda[0] < scl[0] # Start bit: SDA 1->0 while SCL is 1.
def test_read_byte(la: LogicAnalyzer, slave: I2CSlave):
la.capture(2, block=False)
slave.read_byte(REGISTER_ADDRESS)
la.stop()
scl, sda = la.fetch_data()
assert len(scl) == (SCL_START + SCL_WRITE * 2 + SCL_RESTART + SCL_WRITE +
SCL_READ + SCL_STOP)
assert len(sda) == (SDA_START + (SDA_DEVICE_ADDRESS + SDA_NACK) +
(SDA_REGISTER_ADDRESS + SDA_NACK) + SDA_RESTART +
(SDA_DEVICE_ADDRESS + SDA_NACK) + (SDA_READ + SDA_ACK))
def test_configure(la: LogicAnalyzer, master: I2CMaster, slave: I2CSlave):
frequency = 1.25e5
master.configure(frequency)
la.capture(1, block=False)
slave._start(1)
slave._stop()
la.stop()
(scl, ) = la.fetch_data()
write_start = scl[1] # First event is start bit.
write_stop = scl[-2] # Final event is stop bit.
start_to_stop = 8.5 # 9 periods, but initial and final states are the same.
period = (write_stop - write_start) / start_to_stop
assert (period * MICROSECONDS)**-1 == pytest.approx(frequency, rel=RELTOL)
def __init__(self, device: SerialHandler = None):
self._device = device if device is not None else SerialHandler()
self._mcp4728 = I2CSlave(self._ADDRESS, self._device)
self._pv1 = VoltageSource(self._mcp4728, "PV1")
self._pv2 = VoltageSource(self._mcp4728, "PV2")
self._pv3 = VoltageSource(self._mcp4728, "PV3")
self._pcs = CurrentSource(self._mcp4728)
def slave(handler: SerialHandler) -> I2CSlave:
handler._logging = True
return I2CSlave(ADDRESS, device=handler)
def test_ping_slave(slave: I2CSlave):
assert not slave.ping()