def test_vector_type():
vt = VectorType(SIntType(Width(8)), 16)
serialize_equal(vt, "SInt<8>[16]")
vt = VectorType(UIntType(Width(8)), 16)
serialize_equal(vt, "UInt<8>[16]")
vt = VectorType(vt, 32)
serialize_equal(vt, "UInt<8>[16][32]")
vt = VectorType(VectorType(VectorType(vt, 42), 7), 9)
serialize_equal(vt, "UInt<8>[16][32][42][7][9]")
def convert_expr(mi: ModuleInst):
if mi.module_name not in Context.modules:
from .conv_module import convert_module
convert_module(mi.packed_module)
module = Context.modules[mi.module_name]
name = NameGetter.get(mi.id)
ref = Reference(name, ports_to_bundle_type(module.ports))
stmts = [
DefInstance(name, mi.module_name),
Connect(SubField(ref, 'clock', ClockType()),
Reference('clock', ClockType())),
Connect(SubField(ref, 'reset', UIntType(Width(1))),
Reference('reset', UIntType(Width(1))))
]
Context.expr_obj_id_to_ref[id(mi)] = ref
return stmts, ref
def convert_ports(raw_ports: Dict[str, Union[Input, Output]]):
ports = [InputPort('clock', ClockType()),
InputPort('reset', UIntType(Width(1)))]
for k, v in raw_ports.items():
p = InputPort if v.port_dir == 'input' else OutputPort
ports.append(p(k, convert_type(v.hcl_type)))
return ports
def test_sint_literal():
si = SIntLiteral(10, Width(5))
assert check(si)
serialize_equal(si, 'SInt<5>("ha")')
si = SIntLiteral(-10, Width(5))
assert check(si)
serialize_equal(si, 'SInt<5>("h-a")')
si = SIntLiteral(1023, Width(11))
assert check(si)
serialize_equal(si, 'SInt<11>("h3ff")')
si = SIntLiteral(-1023, Width(11))
assert check(si)
serialize_equal(si, 'SInt<11>("h-3ff")')
si = SIntLiteral(10, Width(4))
assert not check(si)
si = SIntLiteral(-10, Width(4))
assert not check(si)
si = SIntLiteral(10, Width(5))
si.tpe = UnknownType()
assert not check(si)
def test_bundle_type():
bd = BundleType([
Field("a", UIntType(Width(8))),
Field("b", UIntType(Width(8))),
Field("c", UIntType(Width(8)), True),
])
serialize_equal(bd, "{a : UInt<8>, b : UInt<8>, flip c : UInt<8>}")
vt = VectorType(UIntType(Width(8)), 16)
bd = BundleType([
Field("a", vt),
Field("b", UIntType(Width(8)), True),
Field("c", VectorType(vt, 32)),
])
serialize_equal(
bd, "{a : UInt<8>[16], flip b : UInt<8>, c : UInt<8>[16][32]}")
# TODO: Is it valid?
bd = BundleType([
Field(
"l1",
BundleType([
Field("l2", BundleType([Field("l3", UIntType(Width(8)),
True)])),
Field("vt", vt),
]))
])
serialize_equal(bd, "{l1 : {l2 : {flip l3 : UInt<8>}, vt : UInt<8>[16]}}")
def test_uint_literal():
ui = UIntLiteral(10, Width(4))
assert check(ui)
serialize_equal(ui, 'UInt<4>("ha")')
ui = UIntLiteral(-10, Width(5))
assert not check(ui)
ui = UIntLiteral(1023, Width(10))
assert check(ui)
serialize_equal(ui, 'UInt<10>("h3ff")')
ui = UIntLiteral(-1023, Width(11))
assert not check(ui)
ui = UIntLiteral(10, Width(3))
assert not check(ui)
ui = UIntLiteral(-10, Width(4))
assert not check(ui)
ui = UIntLiteral(10, Width(3))
ui.tpe = UnknownType()
assert not check(ui)
def test_sint_type():
serialize_equal(SIntType(Width(8)), "SInt<8>")
serialize_equal(SIntType(Width(32)), "SInt<32>")
def test_uint_type():
serialize_equal(UIntType(Width(8)), "UInt<8>")
serialize_equal(UIntType(Width(32)), "UInt<32>")
def convert_type(uint: UIntT):
return UIntType(Width(uint.width))
def convert_type(sint: SIntT):
return SIntType(Width(sint.width))