def randomEnProc():
# small space at start to modify agents when they are inactive
yield Timer(timeQuantum // 4)
while True:
en = random.random() < 0.5
if agent.getEnable() != en:
agent.setEnable(en)
delay = int(random.random() * 2) * timeQuantum
yield Timer(delay)
def data_collector():
yield Timer(CLK_PERIOD // 2)
assert sim.now == CLK_PERIOD // 2
val = io.val
while True:
yield Timer(CLK_PERIOD)
yield WaitCombStable()
data.append((sim.now, int(val.read())))
def get_clk_driver(sim: HdlSimulator, clk, clk_period):
while True:
yield WaitWriteOnly()
clk.write(0)
yield Timer(clk_period // 2)
yield WaitWriteOnly()
clk.write(1)
yield Timer(clk_period // 2)
def monitorWithTimer(self):
if self.initPending and self.initDelay:
yield Timer(self.initDelay)
self.initPending = False
# if there is no clk, we have to manage periodic call by our self
while True:
yield WaitCombRead()
if self._enabled and self.notReset():
d = self.get_data()
self.data.append(d)
yield Timer(self.delay)
def driver(self):
half_period = Timer(self.bit_period // 2)
period = Timer(self.bit_period)
intf = self.intf
yield half_period
while True:
if self.getEnable() and self.data:
ch = self.data.popleft()
intf.write(self.START_BIT)
yield period
for i in range(8):
intf.write((ch >> i) & 0b1)
yield period
intf.write(self.STOP_BIT)
yield period
def driver(self):
sig = self.intf
yield WaitWriteOnly()
sig.write(0)
yield Timer(self.initWait)
while True:
halfPeriod = self.period // 2
yield Timer(halfPeriod)
yield WaitWriteOnly()
sig.write(1)
yield Timer(halfPeriod)
yield WaitWriteOnly()
sig.write(0)
def driverWithTimer(self):
if self.initPending:
if self.initDelay:
yield Timer(self.initDelay)
self.initPending = False
# if clock is specified this function is periodically called every
# clk tick
while True:
yield WaitWriteOnly()
if self._enabled and self.data and self.notReset():
yield WaitWriteOnly()
if self._enabled:
d = self.data.popleft()
self.set_data(d)
yield Timer(self.delay)
def driver(self):
sig = self.intf
yield WaitWriteOnly()
sig.write(1)
yield Timer(self.initDelay)
yield WaitWriteOnly()
sig.write(0)
def get_pull_up_driver(sim: HdlSimulator, sig, delay):
yield WaitWriteOnly()
sig.write(0)
yield Timer(delay)
assert sim.now == delay
yield WaitWriteOnly()
sig.write(1)
def data_collect():
for d_ref in test_data:
yield WaitCombRead()
d = io.outp.read()
d = int(d)
r_data.append(d)
self.assertEqual(d, d_ref)
yield Timer(CLK_PERIOD)
def driver(self):
o = self.o
high = self.pullMode
low = not self.pullMode
halfPeriod = self.period // 2
yield WaitWriteOnly()
o.write(low)
self.t.write(1)
while True:
yield Timer(halfPeriod)
yield WaitWriteOnly()
o.write(high)
yield Timer(halfPeriod)
yield WaitWriteOnly()
o.write(low)
def driver(self):
assert isinstance(self.period, int)
assert isinstance(self.initWait, int)
sig = self.intf
yield WaitWriteOnly()
sig.write(0)
yield Timer(self.initWait)
while True:
halfPeriod = self.period // 2
yield Timer(halfPeriod)
yield WaitWriteOnly()
sig.write(1)
yield Timer(halfPeriod)
yield WaitWriteOnly()
sig.write(0)
def onTWriteCallback(self):
while True:
yield Edge(self.t, self.o)
if self.getEnable():
# if we are this signal was update by change of some memory we can not write in this
# time slot and we have to wait for another
if self.sim._current_time_slot.write_only is DONE:
yield Timer(1)
yield from self.monitor()
def get_rst_driver(sim: HdlSimulator, rst, delay):
yield WaitWriteOnly()
assert sim.now == 0
rst.write(1)
yield Timer(delay)
assert sim.now == delay
yield WaitWriteOnly()
assert sim.now == delay
rst.write(0)
def dataReader(self):
yield Timer(1)
if self.readPending:
yield WaitCombRead()
d = self.intf.data.read()
self.data.append(d)
if self.readPending_invalidate:
self.readPending = False
if not self.readPending and not self._enabled:
self.dataWriter.setEnable(False)
def monitor(self):
"""
Handle read/write request on this interfaces
This method is executed on clock edge.
This means that the read data should be put on dout after clock edge.
"""
intf = self.intf
yield WaitCombStable()
if self.notReset():
en = intf.en.read()
en = int(en)
if en:
we = intf.we.read()
we = int(we)
addr = intf.addr.read()
if we:
data = intf.din.read()
self.onWriteReq(addr, data)
else:
self.onReadReq(addr)
if self.requests:
req = self.requests.popleft()
t = req[0]
addr = req[1]
if t == READ:
v = self.mem.get(addr.val, None)
yield Timer(1)
yield WaitWriteOnly()
intf.dout.write(v)
else:
assert t == WRITE
# yield WaitWriteOnly()
# intf.dout.write(None)
yield Timer(1)
# after clock edge
yield WaitWriteOnly()
self.mem[addr.val] = req[2]
def dataWriter(self):
# delay data litle bit to have nicer wave
# otherwise wirte happens before next clk period
# and it means in 0 time and we will not be able to see it in wave
yield Timer(1)
yield WaitWriteOnly()
self.intf.data.write(self.lastData)
if self.lastData_invalidate:
self.lastData = None
if not self._enabled:
self.dataWriter.setEnable(False)
def monitor(self):
half_period = Timer(self.bit_period // 2)
period = Timer(self.bit_period)
intf = self.intf
yield half_period
while True:
while True:
if not self.getEnable():
yield period
continue
yield WaitTimeslotEnd()
d = intf.read()
if int(d) == self.START_BIT:
break
else:
yield half_period
for _ in range(8):
yield period
yield WaitTimeslotEnd()
d = intf.read()
self.char_buff.append(d)
d = int(d)
if d == self.STOP_BIT:
# correctly received char
self.char_buff.clear()
ch = 0
for b in reversed(self.char_buff):
ch <<= 1
ch |= int(b)
yield period
else:
# received data is in wrong format, discard it
self.char_buff.clear()
yield half_period
def get_pull_up_driver_with_reset(sim: HdlSimulator, sig, reset, clk_period):
exp_t = 0
yield WaitWriteOnly()
sig.write(0)
assert sim.now == exp_t
while True:
yield WaitCombRead()
if not reset.read():
assert sim.now == exp_t
yield WaitWriteOnly()
sig.write(1)
return
else:
yield Timer(clk_period)
exp_t += clk_period
def monitor(self):
# set wait signal
# if en == 1 take data
intf = self.intf
yield WaitWriteOnly()
intf.wait.write(0)
yield WaitCombStable()
# wait for potential update of en
en = intf.en.read()
try:
en = int(en)
except ValueError:
raise AssertionError(self.sim.now, intf,
"en signal in invalid state")
if en:
yield Timer(CLK_PERIOD / 10)
yield WaitCombRead()
self.data.append(self.get_data())
def driver(self):
"""
Drive 'o' and 't' from data buffer.
One step if not selfSynchronization else infinite loop.
"""
while True:
yield WaitWriteOnly()
if self.data:
o = self.data.popleft()
if o == NOP:
t = 0
o = 0
else:
t = 1
self.o.write(o)
self.t.write(t)
if self.selfSynchronization:
yield Timer(CLK_PERIOD)
else:
break
def data_feed():
for d in test_data:
yield WaitWriteOnly()
io.inp.write(d)
yield Timer(CLK_PERIOD)