def __init__(self, pin=146):
if not pin in self.VALID_PINS:
raise Exception("Gpio: invalid pin:"+str(pin)+" not in "+str(self.VALID_PINS))
self.pin = pin
# mux pin, attaching gpio to the pin
pydevmem.write(self.MUX_ADDR[pin], self.MUX_VAL[pin], self.MUX_MASK[pin])
#pydevmem.write(self.muxRegs[self.pin], self.muxVals[self.pin], self.muxMasks[self.pin])
# enable output
pydevmem.write(self.OE_ADDR[pin], 0x00000000, self.BIT_MASK[pin])
#pydevmem.write(self.oeReg[self.pin], 0x00000000, self.masks[self.pin])
print "gpio created on pin",self.pin
def __init__(self, pin=146):
if not pin in self.VALID_PINS:
raise Exception("Gpio: invalid pin:" + str(pin) + " not in " +
str(self.VALID_PINS))
self.pin = pin
# mux pin, attaching gpio to the pin
pydevmem.write(self.MUX_ADDR[pin], self.MUX_VAL[pin],
self.MUX_MASK[pin])
#pydevmem.write(self.muxRegs[self.pin], self.muxVals[self.pin], self.muxMasks[self.pin])
# enable output
pydevmem.write(self.OE_ADDR[pin], 0x00000000, self.BIT_MASK[pin])
#pydevmem.write(self.oeReg[self.pin], 0x00000000, self.masks[self.pin])
print "gpio created on pin", self.pin
def __init__(self, pin=10):
if not pin in self.VALID_PINS:
raise Exception("invalid OmapPwm pin: "+str(pin)+" not in "+str(self.VALID_PINS))
self.pin = pin
# enable 32k clock for pin
pydevmem.write(self.CLKSEL_ADDR[pin], 0xffffffff, self.CLKSEL_MASK[pin])
# enable interface clock (ICLK)
pydevmem.write(self.ICLKEN_ADDR[pin], 0xffffffff, self.ICLKEN_MASK[pin])
# enable functional clock (FCLK)
pydevmem.write(self.FCLKEN_ADDR[pin], 0xffffffff, self.FCLKEN_MASK[pin])
# pause to allow changes to settle
time.sleep(1)
# disable timer (TCLR)
pydevmem.write(self.TCLR_ADDR[pin], self.TCLR_OFF)
# set mux (MUX)
pydevmem.write(self.MUX_ADDR[pin], self.MUX_VAL[pin], self.MUX_MASK[pin])
def __init__(self, pin=10):
if not pin in self.VALID_PINS:
raise Exception("invalid OmapPwm pin: " + str(pin) + " not in " +
str(self.VALID_PINS))
self.pin = pin
# enable 32k clock for pin
pydevmem.write(self.CLKSEL_ADDR[pin], 0xffffffff,
self.CLKSEL_MASK[pin])
# enable interface clock (ICLK)
pydevmem.write(self.ICLKEN_ADDR[pin], 0xffffffff,
self.ICLKEN_MASK[pin])
# enable functional clock (FCLK)
pydevmem.write(self.FCLKEN_ADDR[pin], 0xffffffff,
self.FCLKEN_MASK[pin])
# pause to allow changes to settle
time.sleep(1)
# disable timer (TCLR)
pydevmem.write(self.TCLR_ADDR[pin], self.TCLR_OFF)
# set mux (MUX)
pydevmem.write(self.MUX_ADDR[pin], self.MUX_VAL[pin],
self.MUX_MASK[pin])
def set_match(self, value):
pydevmem.write(self.TMAR_ADDR[self.pin], value)
def set_load(self, value):
pydevmem.write(self.TLDR_ADDR[self.pin], value)
def disable(self):
pydevmem.write(self.TCLR_ADDR[self.pin], self.TCLR_OFF)
def enable(self):
# set the counter (CRR) to it's highest value, this makes the counter overflow
# on the first clock cycle, bringing the output high
pydevmem.write(self.TCRR_ADDR[self.pin], 0xffffffff)
pydevmem.write(self.TCLR_ADDR[self.pin], self.TCLR_ON)
def set_output(self, level):
pydevmem.write(self.DATA_ADDR[self.pin], level,
self.BIT_MASK[self.pin])
#pydevmem.write(self.dataOut[self.pin], level, self.masks[self.pin])
print "set output to", level
def set_output(self, level):
pydevmem.write(self.DATA_ADDR[self.pin], level, self.BIT_MASK[self.pin])
#pydevmem.write(self.dataOut[self.pin], level, self.masks[self.pin])
print "set output to",level
def set_match(self, value):
pydevmem.write(self.TMAR_ADDR[self.pin], value)
def set_load(self, value):
pydevmem.write(self.TLDR_ADDR[self.pin], value)
def disable(self):
pydevmem.write(self.TCLR_ADDR[self.pin], self.TCLR_OFF)
def enable(self):
# set the counter (CRR) to it's highest value, this makes the counter overflow
# on the first clock cycle, bringing the output high
pydevmem.write(self.TCRR_ADDR[self.pin], 0xffffffff)
pydevmem.write(self.TCLR_ADDR[self.pin], self.TCLR_ON)