def test_directed_dict_dflt(sim_cls):
addr = list(range(0, 20, 2))
data = {i: i + 100 for i in addr}
res = [data[i] if i in data else 0 for i in range(20)]
directed(drv(t=Uint[8], seq=range(20)),
f=rom(sim_cls=sim_cls, data=data, dtype=Uint[8], dflt=0),
ref=res)
sim()
def test_directed_dict(sim_cls):
addr = list(range(0, 20, 2))
data = {i: i + 100 for i in addr}
res = list(data.values())
directed(drv(t=Uint[8], seq=addr),
f=rom(sim_cls=sim_cls, data=data, dtype=Uint[8]),
ref=res)
sim()
def funclut(x: Fixpnumber, *, f, precision=b'x.width', dtype=None):
'''Implement arbitrary 1 input parameter function as Lookup-table for
integers. f is arbitrary function e.g. math.sqrt, precision is a number of
bits the function result will be represented with,
sqrt_lut: x | funclut(f=math.sqrt, precision=4)
'''
din_t = x.dtype
step = 2**(-din_t.fract)
w_din = len(din_t)
def gen_vals_signed():
for i in range(2**w_din):
if i < (1 << (w_din - 1)):
yield f(step * i)
else:
yield f(step * (i - (1 << w_din)))
def gen_vals_unsigned():
for i in range(2**w_din):
yield f(step * i)
def gen_vals():
if din_t.signed:
yield from gen_vals_signed()
else:
yield from gen_vals_unsigned()
if dtype is None:
float_res_list = list(gen_vals())
vmin = min(map(round, float_res_list))
vmax = max(map(round, float_res_list))
if vmin < 0:
dtype = Fixp[bitw(
max(2 * abs(vmin), 2 * (vmax) +
(1 if vmax > 0 else 0))), precision]
else:
dtype = Ufixp[bitw(max(vmax, vmin)), precision]
lut_list = [dtype(v) for v in float_res_list]
else:
lut_list = [dtype(v) for v in gen_vals()]
dout = x >> Uint[w_din] | rom(data=lut_list, dtype=dtype)
return dout
def stddev(ii_s: Queue[Uint['w_ii'], 2], sii_s: Queue[Uint['w_sii'], 2], *,
casc_hw):
ii_sum = ii_s | frame_sum | dreg_sp
ii_sum_squared = ii_sum[0] * ii_sum[0]
sii_sum = sii_s | frame_sum | dreg_sp
sii_mult1 = sii_sum[0] * (casc_hw.frame_size[0] - 1)
sii_mult2 = sii_mult1 * (casc_hw.frame_size[1] - 1)
sub_s = sii_mult2 - ii_sum_squared
sqrt_addr = sub_s >> casc_hw.sqrt_shift | Uint[8]
stddev_res = sqrt_addr | rom(data=casc_hw.sqrt_mem,
dtype=Uint[casc_hw.w_sqrt])
return stddev_res
def feature_addr(stage_counter: Queue[Uint['w_stage_addr'], 1], rst_in: Unit,
*, casc_hw):
rst_in | local_rst
stage_counter = stage_counter
feature_num_in_stage = stage_counter[0] | rom(
data=casc_hw.features_stage_count_mem,
dtype=Uint[casc_hw.w_features_stage_count])
cnt_end, cnt_start = feature_num_in_stage | Tuple[
Uint[casc_hw.w_features_stage_count / 2],
Uint[casc_hw.w_features_stage_count / 2]]
feature_cnt = ccat(cnt_start, cnt_end, 1) | rng
stage_counter = stage_counter | cart_sync_with(feature_cnt)
dout_eot = ccat(feature_cnt[1], stage_counter[1]) | Uint[2]
feature_cnt = ccat(
feature_cnt[0],
dout_eot) | Queue[Uint[int(casc_hw.w_features_stage_count / 2)], 2]
return feature_cnt | dreg