def test_dout_queue_lvl_2_cosim(cosim_cls): verif(drv(t=Queue[Uint[4], 3], seq=[[[list(range(2)) for _ in range(2)] for _ in range(2)]]), f=flatten(sim_cls=cosim_cls), ref=flatten(name='ref_model')) sim()
def test_directed_two_inputs(cosim_cls): verif(drv(t=T_DIN_SEP, seq=[list(range(9)), list(range(5))]), drv(t=T_CFG, seq=[2, 3]), f=take(sim_cls=cosim_cls), ref=take(name='ref_model')) sim()
def test_dout_queue_lvl_2_no_datacosim(cosim_cls): verif(drv(t=Queue[Unit, 3], seq=[[[[Unit() for _ in range(2)] for _ in range(2)] for _ in range(2)]]), f=flatten(sim_cls=cosim_cls), ref=flatten(name='ref_model')) sim()
def test_directed_cosim(cosim_cls, din_delay, dout_delay): dut = get_decoupled_dut(dout_delay, replicate) verif(drv(t=T_DIN, seq=SEQUENCE) | delay_rng(din_delay, din_delay), f=dut(sim_cls=cosim_cls), ref=replicate(name='ref_model'), delays=[delay_rng(dout_delay, dout_delay)]) sim()
def test_unsigned_overflow_cosim(cosim_cls): seq = [(0x1, 0x2), (0x1, 0x1), (0xf, 0x1)] verif(drv(t=Tuple[Uint[4], Uint[2]], seq=seq), f=sub(sim_cls=cosim_cls), ref=sub(name='ref_model')) sim()
def test_unsigned_overflow_cosim(cosim_cls): seq = [(0x1, 0xf), (0x2, 0xe), (0x3, 0xd)] verif(drv(t=Tuple[Uint[2], Uint[4]], seq=seq), f=mul(sim_cls=cosim_cls), ref=mul(name='ref_model')) sim()
def test_directed_cosim(cosim_cls, lvl, din_delay, dout_delay): seq = DIR_SEQ dut = get_dut(dout_delay) verif(drv(t=T_DIN, seq=seq) | delay_rng(din_delay, din_delay), f=dut(sim_cls=cosim_cls, lvl=lvl), ref=qcnt(name='ref_model', lvl=lvl), delays=[delay_rng(dout_delay, dout_delay)]) sim()
def test_qfilt_union_delay(cosim_cls, din_delay, dout_delay, sel): dut = get_dut(dout_delay) verif(drv(t=queue_din, seq=[directed_seq, directed_seq]) | delay_rng(din_delay, din_delay), f=dut(sim_cls=cosim_cls, fixsel=sel), ref=filt(name='ref_model', fixsel=sel), delays=[delay_rng(dout_delay, dout_delay)]) sim()
def test_signed_unsigned_cosim(cosim_cls): seq = [(0x1, 0xf), (-0x2, 0xf), (0x1, 0x0), (-0x2, 0x0)] verif(drv(t=Tuple[Int[2], Uint[4]], seq=seq), f=sub(sim_cls=cosim_cls), ref=sub(name='ref_model')) sim()
def test_signed_cosim(cosim_cls): seq = [(0x1, 0x7), (-0x2, 0x7), (0x1, -0x8), (-0x2, -0x8)] verif(drv(t=Tuple[Int[2], Int[4]], seq=seq), f=mul(sim_cls=cosim_cls), ref=mul(name='ref_model')) sim()
def test_unsigned_cosim(cosim_cls): seq = [(0x6, 0x2), (0x5, 0x2), (0x4, 0x3)] verif(drv(t=Tuple[Uint[4], Uint[2]], seq=seq), f=mod(sim_cls=cosim_cls), ref=mod(name='ref_model')) sim()
def test_cosim(cosim_cls, din_delay, dout_delay): verif(drv(t=Uint[8], seq=[0]) | delay_rng(din_delay, din_delay), drv(t=Queue[Uint[8]], seq=[list(range(10))]) | delay_rng(din_delay, din_delay), f=cart(sim_cls=cosim_cls), ref=cart(name='ref_model'), delays=[delay_rng(dout_delay, dout_delay)]) sim()
def test_random_cosim(cosim_cls, din_delay, dout_delay): skip_ifndef('RANDOM_TEST') seq = RANDOM_SEQ dut = get_dut(dout_delay) verif(drv(t=T_DIN, seq=seq) | delay_rng(din_delay, din_delay), f=dut(sim_cls=cosim_cls), ref=qcnt(name='ref_model'), delays=[delay_rng(dout_delay, dout_delay)]) sim()
def test_queue_unit(cosim_cls, lvl): # sequence represents eot values # cast to Queue[Unit] after driver seq = [0, 0, 1, 2, 1, 2, 3] verif(drv(t=Uint[8], seq=seq) >> Queue[Unit, lvl], f=dreg(sim_cls=cosim_cls), ref=dreg(name='ref_model')) sim()
def test_queue_tuple(cosim_cls, din_delay, dout_delay): seq = [[(0, 1), (4, 0), (1, 1)], [(1, 1), (2, 0), (3, 1), (4, 0)]] dut = get_dut(dout_delay) verif(drv(t=Queue[Tuple[Uint[16], Int[2]]], seq=seq) | delay_rng(din_delay, din_delay), f=dut(sim_cls=cosim_cls), ref=dreg(name='ref_model'), delays=[delay_rng(dout_delay, dout_delay)]) sim()
def test_replicate_queue(cosim_cls, din_delay, dout_delay): dut = get_decoupled_dut(dout_delay, replicate_while) verif(drv(t=Bool, seq=[1, 1, 0] * 5), drv(t=Queue[Uint[16]], seq=[list(range(5))]) | delay_rng(din_delay, din_delay), f=dut(sim_cls=cosim_cls), ref=replicate_while(name='ref_model'), delays=[delay_rng(dout_delay, dout_delay)]) sim()
def test_cosim_active(cosim_cls, din_delay, dout_delay): no = 4 dut = get_dut(dout_delay) verif(drv(t=TDin[Uint[8], no, 4], seq=[((8, ) * no, 3), ((2, ) * no, 4), ((1, ) * no, 1)]) | delay_rng(din_delay, din_delay), f=dut(sim_cls=cosim_cls), ref=serialize(name='ref_model'), delays=[delay_rng(dout_delay, dout_delay)]) sim()
def test_cosim(din_delay, dout_delay): from pygears.sim.modules import SimVerilated seq = list(range(1, 10)) verif(drv(t=Uint[16], seq=seq) | delay_rng(0, din_delay), f=pipe(name='dut', length=8), ref=pipe(length=8, sim_cls=SimVerilated), delays=[delay_rng(0, dout_delay)], check_timing=True) sim()
def test_cosim(cosim_cls, din_delay, dout_delay): brick_size = 4 seq_list = [1, 2, 3, 4] dut = get_dut(dout_delay) verif(drv(t=Array[Uint[16], brick_size], seq=[(i, ) * brick_size for i in seq_list]) | delay_rng(din_delay, din_delay), f=dut(sim_cls=cosim_cls), ref=serialize(name='ref_model'), delays=[delay_rng(dout_delay, dout_delay)]) sim()
def test_queue_3(cosim_cls, din_delay, dout_delay): verif(drv(t=Queue[Uint[2]], seq=[[0, 1], [2, 3]]) | delay_rng(din_delay[0], din_delay[0]), drv(t=Queue[Uint[3]], seq=[[4, 5], [6, 7]]) | delay_rng(din_delay[1], din_delay[1]), drv(t=Queue[Uint[8]], seq=[[8, 9], [10, 11]]) | delay_rng(din_delay[2], din_delay[2]), f=ccat(sim_cls=cosim_cls), ref=ccat(name='ref_model'), delays=[delay_rng(dout_delay, dout_delay)]) sim()
def test_cosim_zipsync_both_queue(cosim_cls, din0_delay, din1_delay, dout0_delay, dout1_delay): verif(drv(t=Queue[Uint[8], 2], seq=[[list(range(10)) for _ in range(2)]]) | delay_rng(din0_delay, din0_delay), drv(t=Queue[Uint[8], 2], seq=[[list(range(10)) for _ in range(2)]]) | delay_rng(din1_delay, din1_delay), f=zip_sync(sim_cls=cosim_cls), ref=zip_sync(name='ref_model'), delays=[ delay_rng(dout0_delay, dout0_delay), delay_rng(dout1_delay, dout1_delay) ]) sim()
def test_socket_rand_cons(): skip_ifndef('SIM_SOCKET_TEST', 'RANDOM_TEST') cons = [] cons.append( randomize(T_DIN, 'din', eot_cons=['data_size == 50', 'trans_lvl1[0] == 4'])) verif(drv(t=T_DIN, seq=rand_seq('din', 30)), f=qcnt(sim_cls=partial(SimSocket, run=True)), ref=qcnt(name='ref_model')) sim(extens=[partial(SVRandSocket, cons=cons)])
def test_basic(cosim_cls): seq_op1 = [1, 2, 3] seq_op2 = [2, 2, 2] @gear def eq_wrap(op1, op2): return op1 == op2 verif(drv(t=Uint[4], seq=seq_op1), drv(t=Uint[4], seq=seq_op2), f=eq_wrap(sim_cls=cosim_cls), ref=eq(name='ref_model')) sim(check_activity=False)
def test_basic(cosim_cls): seq_op1 = [1, 2, 3] seq_op2 = [2, 2, 2] @gear def xor_wrap(op1, op2): return op1 ^ op2 verif( drv(t=Uint[4], seq=seq_op1), drv(t=Uint[4], seq=seq_op2), f=xor_wrap(sim_cls=cosim_cls), ref=xor(name='ref_model')) sim()
def test_random_constrained(): skip_ifndef('SIM_SOCKET_TEST', 'RANDOM_TEST') cnt = 5 # cons.append(randomize(T_CFG, 'cfg', cons=['cfg == 2'])) stim = [] stim.append(drv(t=T_DIN_SEP, seq=randomize(T_DIN_SEP, 'din', cnt=cnt))) stim.append( drv(t=T_CFG, seq=randomize(T_CFG, 'cfg', cons=['cfg < 20', 'cfg > 0'], cnt=cnt))) verif(*stim, f=clip, ref=clip(name='ref_model')) cosim('/clip', 'xsim', run=False) sim()
def test_random(cosim_cls): skip_ifndef('RANDOM_TEST') cfg_seq = [] din_seq = [] cfg_num = random.randint(2, 10) for _ in range(cfg_num): cfg_seq.append(random.randint(1, 10)) din_seq.append(list(range(random.randint(1, 10)))) verif( drv(t=T_DIN_SEP, seq=din_seq), drv(t=T_CFG, seq=cfg_seq), f=clip(sim_cls=cosim_cls), ref=clip(name='ref_model')) sim()
def test_socket_cosim_rand(): skip_ifndef('SIM_SOCKET_TEST', 'RANDOM_TEST') din_num = 3 cons = [] for i in range(din_num): cons.append(randomize(T_DIN, f'din{i}', eot_cons=['data_size == 10'])) stim = [] for i in range(din_num): stim.append(drv(t=T_DIN, seq=rand_seq(f'din{i}', 30))) verif(*stim, f=qinterlace(sim_cls=partial(SimSocket, run=True)), ref=qinterlace(name='ref_model')) sim(extens=[partial(SVRandSocket, cons=cons)])
def test_random(sim_cls): skip_ifndef('RANDOM_TEST') din_num = 3 stim = [] for _ in range(din_num): stim.append( drv(t=T_DIN, seq=[ list(range(random.randint(1, 10))), list(range(random.randint(1, 10))) ])) verif(*stim, f=qinterlace(sim_cls=sim_cls), ref=qinterlace(name='ref_model')) sim()
def cast_cosim_test(src_type, cast_type, seq, expected, module=cast_gear): report = verif(drv(t=src_type, seq=seq), f=module(sim_cls=SimVerilated, t=cast_type), ref=module(name='ref_model', t=cast_type), make_report=True) sim() for e, rep in zip(expected, report[0]): assert e == rep['items'][0]
def test_2_inputs(cosim_cls): din0_delay = (1, 1) din1_delay = (2, 2) dout_delay = (3, 3) assert dout_delay[0] == dout_delay[ 1], 'Simulation cannot check random delays for this type of gear' seq0 = list(range(10)) seq1 = list(range(10, 20)) verif(drv(t=Uint[8], seq=seq0) | delay_rng(*din0_delay), drv(t=Uint[8], seq=seq1) | delay_rng(*din1_delay), f=priority_mux(sim_cls=cosim_cls), ref=priority_mux(name='ref_model'), delays=[delay_rng(*dout_delay)]) sim()