def prefill(din, *, num, dtype):
fill = once(val=dtype(0)) \
| replicate(num) \
| flatten
return priority_mux(fill, din) \
| union_collapse
def test_2_inputs(cosim_cls):
din0_delay = (1, 1)
din1_delay = (2, 2)
dout_delay = (3, 3)
assert dout_delay[0] == dout_delay[
1], 'Simulation cannot check random delays for this type of gear'
seq0 = list(range(10))
seq1 = list(range(10, 20))
verif(drv(t=Uint[8], seq=seq0)
| delay_rng(*din0_delay),
drv(t=Uint[8], seq=seq1)
| delay_rng(*din1_delay),
f=priority_mux(sim_cls=cosim_cls),
ref=priority_mux(name='ref_model'),
delays=[delay_rng(*dout_delay)])
sim()
def test_directed(
cosim_cls,
wr0_delay,
rd0_delay,
wr1_delay,
rd1_delay,
dout_delay,
depth,
):
def wr0_delay_gen():
for _ in range(depth):
yield 0
while True:
yield wr0_delay
w_addr = 3
w_data = 8
wr_req_t = TWrReq[w_addr, Uint[w_data]]
rd_req_t = Uint[w_addr]
req_t = Union[rd_req_t, wr_req_t]
wr0_req_seq = [(i, i * 2) for i in range(depth)]
wr0_init_seq = [(i, 0) for i in range(depth)]
rd0_req_seq = list(range(depth))
rd1_req_seq = list(range(depth))
wr0_req = drv(t=wr_req_t, seq=wr0_init_seq + wr0_req_seq) \
| delay_gen(f=wr0_delay_gen())
rd0_req = drv(t=Uint[w_addr], seq=rd0_req_seq) \
| delay_gen(f=iter([depth])) \
| delay_rng(0, rd0_delay)
req0 = priority_mux(rd0_req, wr0_req)
req1 = ccat(drv(t=Uint[w_addr], seq=rd1_req_seq) \
| req_t.data \
| delay_gen(f=iter([depth])) \
| delay_rng(0, rd1_delay)
, Bool(False)) | req_t
verif(req0,
req1,
f=tdp(name='dut', sim_cls=cosim_cls, depth=depth),
ref=tdp(depth=depth),
delays=[delay_rng(0, dout_delay),
delay_rng(0, 0)])
sim()
def test_queue(sim_cls):
din0_delay = (1, 1)
din1_delay = (2, 2)
din2_delay = (1, 1)
seq0 = [list(range(3)), list(range(2)), list(range(4, 8))]
seq1 = [list(range(7, 8)), list(range(6, 9))]
seq2 = [list(range(0, 2)), list(range(9, 11))]
directed(drv(t=Queue[Uint[4]], seq=seq0)
| delay_rng(*din0_delay),
drv(t=Queue[Uint[4]], seq=seq1)
| delay_rng(*din1_delay),
drv(t=Queue[Uint[4]], seq=seq2)
| delay_rng(*din2_delay),
f=priority_mux(sim_cls=sim_cls),
ref=[[(0, 0), (1, 0), (2, 0)], [(7, 1)], [(0, 0), (1, 0)],
[(6, 1), (7, 1), (8, 1)], [(4, 0), (5, 0), (6, 0), (7, 0)],
[(0, 2), (1, 2)], [(9, 2), (10, 2)]])
sim()
def test_diff_types(sim_cls):
din0_delay = (1, 1)
din1_delay = (2, 2)
din2_delay = (1, 1)
seq0 = list(range(5))
seq1 = [(1, 2), (2, 1), (3, 3), (4, 1), (3, 2)]
seq2 = list(range(3))
directed(drv(t=Uint[4], seq=seq0)
| delay_rng(*din0_delay),
drv(t=Tuple[Uint[8], Uint[3]], seq=seq1)
| delay_rng(*din1_delay),
drv(t=Int[3], seq=seq2)
| delay_rng(*din2_delay),
f=priority_mux(sim_cls=sim_cls),
ref=[(0, 0), ((1, 2), 1), (1, 0), (0, 2), (2, 0), ((2, 1), 1),
(3, 0), (1, 2), (4, 0), ((3, 3), 1), (2, 2), ((4, 1), 1),
((3, 2), 1)])
sim()
def test_uint():
priority_mux(Intf(Uint[8]), Intf(Uint[8]))