def trigtype(self, value):
r = self.reg_base + Trigger._REG_CONFIG
self._instr._accessor_set(
r,
to_reg_unsigned(0,
4,
allow_set=[Trigger.TYPE_EDGE, Trigger.TYPE_PULSE]),
value)
def pulsetype(self, value):
r = self.reg_base + Trigger._REG_CONFIG
self._instr._accessor_set(
r,
to_reg_unsigned(7,
2,
allow_set=[Trigger.PULSE_MIN, Trigger.PULSE_MAX]),
value)
def edge(self, value):
r = self.reg_base + Trigger._REG_CONFIG
self._instr._accessor_set(
r,
to_reg_unsigned(4,
2,
allow_set=[
Trigger.EDGE_RISING, Trigger.EDGE_FALLING,
Trigger.EDGE_BOTH
]), value)
def waveform(self, value):
r = self.reg_base + SweepGenerator._REG_CONFIG
self._instr._accessor_set(
r,
to_reg_unsigned(0,
2,
allow_set=[
SweepGenerator.WAVE_TYPE_SINGLE,
SweepGenerator.WAVE_TYPE_UPDOWN,
SweepGenerator.WAVE_TYPE_SAWTOOTH,
SweepGenerator.WAVE_TYPE_TRIANGLE
]), value)
def duration(self, value):
r1 = self.reg_base + SweepGenerator._REG_DURATION_LSB
r2 = self.reg_base + SweepGenerator._REG_DURATION_MSB
self._instr._accessor_set((r2, r1), to_reg_unsigned(0, 64), value)
def p_gain(self, value):
r = self.reg_base + PID._REG_P_GAIN
self._instr._accessor_set(
r, to_reg_unsigned(0, 25, xform=lambda obj, x: x * (2.0**11)),
value)
elif source == _OSC_SOURCE_DA1:
level = (scales['gain_dac1']) * 16 / deci_gain
elif source == _OSC_SOURCE_DA2:
level = (scales['gain_dac2']) * 16 / deci_gain
else:
level = 1.0
return level
_osc_reg_handlers = {
'source_ch1': (REG_OSC_OUTSEL,
to_reg_unsigned(0,
8,
allow_set=[
_OSC_SOURCE_CH1, _OSC_SOURCE_CH2,
_OSC_SOURCE_DA1, _OSC_SOURCE_DA2,
_OSC_SOURCE_EXT
]), from_reg_unsigned(0, 8)),
'source_ch2': (REG_OSC_OUTSEL,
to_reg_unsigned(8,
8,
allow_set=[
_OSC_SOURCE_CH1, _OSC_SOURCE_CH2,
_OSC_SOURCE_DA1, _OSC_SOURCE_DA2,
_OSC_SOURCE_EXT
]), from_reg_unsigned(8, 8)),
'trig_ch': (REG_OSC_TRIGCTL,
to_reg_unsigned(4,
6,
allow_set=[
super(FIRFilter, self)._on_reg_sync()
# Update local variables with device variables
self._sync_gains_offsets_regs()
self._sync_control_matrix_regs()
_fir_reg_handlers = {
'reset_ch1': (REG_FIR_CONTROL, to_reg_bool(0), from_reg_bool(0)),
'reset_ch2': (REG_FIR_CONTROL, to_reg_bool(1), from_reg_bool(1)),
'filter_en1': (REG_FIR_CONTROL, to_reg_bool(2), from_reg_bool(2)),
'filter_en2': (REG_FIR_CONTROL, to_reg_bool(3), from_reg_bool(3)),
'link': (REG_FIR_CONTROL, to_reg_bool(4), from_reg_bool(4)),
'input_en1': (REG_FIR_CONTROL, to_reg_bool(5), from_reg_bool(5)),
'input_en2': (REG_FIR_CONTROL, to_reg_bool(6), from_reg_bool(6)),
'mon1_source':
(REG_FIR_CONTROL, to_reg_unsigned(8, 3), from_reg_unsigned(8, 3)),
'mon2_source': (REG_FIR_CONTROL, to_reg_unsigned(12, 3),
from_reg_unsigned(12, 3)),
'mon1_clip': (REG_FIR_CONTROL, to_reg_bool(11), from_reg_bool(11)),
'mon2_clip': (REG_FIR_CONTROL, to_reg_bool(15), from_reg_bool(15)),
'output_en1': (REG_FIR_CONTROL, to_reg_bool(16), from_reg_bool(16)),
'output_en2': (REG_FIR_CONTROL, to_reg_bool(17), from_reg_bool(17)),
'input_scale1':
(REG_FIR_IN_SCALE1, to_reg_signed(0, 18, xform=lambda obj, x: x * 2.0**9),
from_reg_signed(0, 18, xform=lambda obj, x: x / (2.0**9))),
'input_scale2':
(REG_FIR_IN_SCALE2, to_reg_signed(0, 18, xform=lambda obj, x: x * 2.0**9),
from_reg_signed(0, 18, xform=lambda obj, x: x / (2.0**9))),
'input_offset1':
(REG_FIR_IN_OFFSET1,
to_reg_signed(
_llb_reg_hdl = {
'_fast_scale':
(REG_LLB_GAINS_SCALING, to_reg_signed(0,
16,
xform=lambda obj, x: x * 2**14),
from_reg_signed(0, 16, xform=lambda obj, x: x / 2**14)),
'_slow_scale': (REG_LLB_GAINS_SCALING,
to_reg_signed(16, 16, xform=lambda obj, x: x * 2**14),
from_reg_signed(16, 16, xform=lambda obj, x: x / 2**14)),
'_aux_scale':
(REG_LLB_AUX_SCALE, to_reg_signed(0, 16, xform=lambda obj, x: x * 2**14),
from_reg_signed(0, 16, xform=lambda obj, x: x / 2**14)),
'scan_amplitude': (REG_LLB_SCAN_SCALE,
to_reg_signed(0, 16, xform=lambda obj, x: x * 2**14),
from_reg_signed(0, 16, xform=lambda obj, x: x / 2**14)),
'fast_scan_enable': (REG_LLB_SCAN_CTRL, to_reg_unsigned(0, 1),
from_reg_unsigned(0, 1)),
'slow_scan_enable': (REG_LLB_SCAN_CTRL, to_reg_unsigned(1, 1),
from_reg_unsigned(1, 1)),
'lo_phase_offset': (REG_LLB_LO_PHASE_OFFSET, to_reg_unsigned(0, 28),
from_reg_unsigned(0, 28)),
'aux_phase_offset': (REG_LLB_AUX_PHASE_OFFSET, to_reg_unsigned(0, 28),
from_reg_unsigned(0, 28)),
'fast_offset': (REG_LLB_OFFSETS_FASTINPUT,
to_reg_signed(0, 18, xform=lambda obj, x: x * 2**15),
from_reg_signed(0, 18, xform=lambda obj, x: x / 2**15)),
'output_offset_ch1': (REG_LLB_OFFSETS_FASTOUTPUT,
to_reg_signed(0,
18,
xform=lambda obj, x: x * (2**15)),
from_reg_signed(0,
commit.__doc__ = MokuInstrument.commit.__doc__
_fra_reg_handlers = {
'loop_sweep': (REG_FRA_ENABLES, to_reg_bool(0), from_reg_bool(0)),
'single_sweep': (REG_FRA_ENABLES, to_reg_bool(1), from_reg_bool(1)),
'sweep_reset': (REG_FRA_ENABLES, to_reg_bool(2), from_reg_bool(2)),
'channel1_en': (REG_FRA_ENABLES, to_reg_bool(3), from_reg_bool(3)),
'channel2_en': (REG_FRA_ENABLES, to_reg_bool(4), from_reg_bool(4)),
'adc1_en': (REG_FRA_ENABLES, to_reg_bool(5), from_reg_bool(5)),
'adc2_en': (REG_FRA_ENABLES, to_reg_bool(6), from_reg_bool(6)),
'dac1_en': (REG_FRA_ENABLES, to_reg_bool(7), from_reg_bool(7)),
'dac2_en': (REG_FRA_ENABLES, to_reg_bool(8), from_reg_bool(8)),
'sweep_freq_min':
((REG_FRA_SWEEP_FREQ_MIN_H, REG_FRA_SWEEP_FREQ_MIN_L),
to_reg_unsigned(0, 48, xform=lambda obj, f: f * _FRA_FREQ_SCALE),
from_reg_unsigned(0, 48, xform=lambda obj, f: f / _FRA_FREQ_SCALE)),
'sweep_freq_delta':
((REG_FRA_SWEEP_FREQ_DELTA_H, REG_FRA_SWEEP_FREQ_DELTA_L),
to_reg_signed(0, 48), from_reg_signed(0, 48)),
'log_en': (REG_FRA_LOG_EN, to_reg_bool(0), from_reg_bool(0)),
'sweep_length': (REG_FRA_SWEEP_LENGTH, to_reg_unsigned(0, 10),
from_reg_unsigned(0, 10)),
'settling_time':
(REG_FRA_HOLD_OFF_L,
to_reg_unsigned(0, 32, xform=lambda obj, t: t * _FRA_FPGA_CLOCK),
from_reg_unsigned(0, 32, xform=lambda obj, t: t / _FRA_FPGA_CLOCK)),
'averaging_time':
(REG_FRA_AVERAGE_TIME,
to_reg_unsigned(0, 32, xform=lambda obj, t: t * _FRA_FPGA_CLOCK),
from_reg_unsigned(0, 32, xform=lambda obj, t: t / _FRA_FPGA_CLOCK)),
def duration(self, value):
r = self.reg_base + Trigger._REG_DURATION
self._instr._accessor_set(r, to_reg_unsigned(0, 32), value)
def ntrigger(self, value):
r = self.reg_base + Trigger._REG_NTRIGGER
self._instr._accessor_set(r, to_reg_unsigned(0, 16), value)
def output_offset(self, value):
r = self.reg_base + PID._REG_OUT_OFFSET
return self._instr._accessor_set(r, to_reg_unsigned(0, 16, value))
def d_fb(self, value):
r = self.reg_base + PID._REG_D_FB
return self._instr._accessor_set(
r, to_reg_unsigned(0, 25, xform=lambda obj, x: x * (2.0**24 - 1)),
value)
def d_gain(self, value):
r = self.reg_base + PID._REG_D_GAIN
return self._instr._accessor_set(r, to_reg_unsigned(0, 25), value)
def logsweep(self, value):
r = self.reg_base + SweepGenerator._REG_CONFIG
self._instr._accessor_set(r, to_reg_unsigned(6, 1, allow_set=[0, 1]),
value)
def step(self, value):
r1 = self.reg_base + SweepGenerator._REG_STEP_LSB
r2 = self.reg_base + SweepGenerator._REG_STEP_MSB
self._instr._accessor_set((r2, r1), to_reg_unsigned(0, 64), value)
def hysteresis(self, value):
r = self.reg_base + Trigger._REG_HYSTERESIS
self._instr._accessor_set(r, to_reg_unsigned(0, 16), value)
level = scales['gain_adc2']
elif (source == _ARB_TRIG_SRC_EXT):
level = 1.0
else:
level = 1.0
return level
_arb_reg_handlers = {
'enable1': (REG_ARB_SETTINGS1, to_reg_bool(0), from_reg_bool(0)),
'phase_rst1': (REG_ARB_SETTINGS1, to_reg_bool(1), from_reg_bool(1)),
'mode1': (REG_ARB_SETTINGS1,
to_reg_unsigned(2,
2,
allow_set=[
_ARB_MODE_125, _ARB_MODE_250, _ARB_MODE_500,
_ARB_MODE_1000
]), from_reg_unsigned(2, 2)),
'interpolation1': (REG_ARB_SETTINGS1, to_reg_bool(4), from_reg_bool(4)),
'trig_source1': (REG_ARB_SETTINGS1,
to_reg_unsigned(5,
5,
allow_set=[
_ARB_TRIG_SRC_CH1, _ARB_TRIG_SRC_CH2,
_ARB_TRIG_SRC_EXT
]), from_reg_unsigned(5, 5)),
'lut_length1':
(REG_ARB_LUT_LENGTH1, to_reg_unsigned(0, 16), from_reg_unsigned(0, 16)),
'dead_value1': (REG_ARB_LUT_LENGTH1,
to_reg_signed(16, 16, xform=lambda obj, r: r * (2.0**15)),
from_reg_signed(16, 16, xform=lambda obj, r: r /
def holdoff(self, value):
r = self.reg_base + Trigger._REG_HOLDOFF
self._instr._accessor_set(r, to_reg_unsigned(0, 32), value)
"""
_utils.check_parameter_valid('set',
ch, [1, 2],
'output channel',
allow_none=True)
if (ch is None) or ch == 1:
self.pm_out1_amplitude = 0
if (ch is None) or ch == 2:
self.pm_out2_amplitude = 0
_pm_siggen_reg_hdl = {
'pm_out1_frequency':
((REG_PM_SG_FREQ1_H, REG_PM_SG_FREQ1_L),
to_reg_unsigned(0, 48, xform=lambda obj, f: f * _PM_SG_FREQSCALE),
from_reg_unsigned(0, 48, xform=lambda obj, f: f / _PM_FREQSCALE)),
'pm_out2_frequency':
((REG_PM_SG_FREQ2_H, REG_PM_SG_FREQ2_L),
to_reg_unsigned(0, 48, xform=lambda obj, f: f * _PM_SG_FREQSCALE),
from_reg_unsigned(0, 48, xform=lambda obj, f: f / _PM_FREQSCALE)),
'pm_out1_amplitude':
(REG_PM_SG_AMP,
to_reg_unsigned(0, 16, xform=lambda obj, a: a / obj._dac_gains()[0]),
from_reg_unsigned(0, 16, xform=lambda obj, a: a * obj._dac_gains()[0])),
'pm_out2_amplitude':
(REG_PM_SG_AMP,
to_reg_unsigned(16, 16, xform=lambda obj, a: a / obj._dac_gains()[1]),
from_reg_unsigned(16, 16, xform=lambda obj, a: a * obj._dac_gains()[1])),
'pm_out1_phase':
((REG_PM_SG_PHASE1_H, REG_PM_SG_PHASE1_L),
'ch1_out_en': (REG_LIA_ENABLES, to_reg_bool(8), from_reg_bool(8)),
'ch2_out_en': (REG_LIA_ENABLES, to_reg_bool(9), from_reg_bool(9)),
'lpf_den': (REG_LIA_ENABLES, to_reg_bool(10), from_reg_bool(10)),
'pid1_ch1_den': (REG_LIA_ENABLES, to_reg_bool(11), from_reg_bool(11)),
'ch1_pid1_bypass': (REG_LIA_ENABLES, to_reg_bool(13), from_reg_bool(13)),
'ch1_signal_en': (REG_LIA_ENABLES, to_reg_bool(14), from_reg_bool(14)),
'ch1_pid1_int_dc_pole':
(REG_LIA_ENABLES, to_reg_bool(16), from_reg_bool(16)),
'ch2_signal_en': (REG_LIA_ENABLES, to_reg_bool(17), from_reg_bool(17)),
'ext_demod': (REG_LIA_ENABLES, to_reg_bool(18), from_reg_bool(18)),
'lo_PLL': (REG_LIA_ENABLES, to_reg_bool(19), from_reg_bool(19)),
'filt_bypass1': (REG_LIA_ENABLES, to_reg_bool(21), from_reg_bool(21)),
'filt_bypass2': (REG_LIA_ENABLES, to_reg_bool(22), from_reg_bool(22)),
'pid_ch_select': (REG_LIA_ENABLES, to_reg_bool(23), from_reg_bool(23)),
'aux_select':
(REG_LIA_ENABLES, to_reg_unsigned(26, 2), from_reg_unsigned(26, 2)),
'input_gain_select': (REG_LIA_ENABLES, to_reg_unsigned(28, 2),
from_reg_unsigned(28, 2)),
'ch1_pid1_in_offset':
(REG_LIA_IN_OFFSET1,
to_reg_signed(16, 16, xform=lambda obj, x: x / obj._dac_gains()[0]),
from_reg_signed(16, 16, xform=lambda obj, x: x * obj._dac_gains()[0])),
'ch1_pid1_out_offset':
(REG_LIA_OUT_OFFSET1,
to_reg_signed(16, 16, xform=lambda obj, x: x / obj._dac_gains()[0]),
from_reg_signed(16, 16, xform=lambda obj, x: x * obj._dac_gains()[0])),
'main_offset':
(REG_LIA_OUT_OFFSET1,
to_reg_signed(0, 16, xform=lambda obj, x: x / obj._dac_gains()[0]),
from_reg_signed(0, 16, xform=lambda obj, x: x * obj._dac_gains()[0])),
'lpf_pidgain': (REG_LIA_PIDGAIN1,
def set_samplerate(self, factor):
d_wdfmuxsel = 0
d_outmuxsel = 0
d_cic1_dec = 0
d_cic1_bitshift = 0
d_cic2_dec = 0
d_cic2_bitshift = 0
i_muxsel = 0
i_ratechange_cic2 = 0
i_interprate_cic2 = 0
i_bitshift_cic2 = 0
i_ratechange_cic1 = 0
i_bitshift_cic1 = 0
i_interprate_cic1 = 0
i_highrate_wdf1 = 0
i_highrate_wdf2 = 0
if factor == 1:
d_outmuxsel = 0
i_muxsel = 0
elif factor == 2:
d_wdfmuxsel = 0
d_outmuxsel = 1
i_muxsel = 1
i_highrate_wdf1 = 0
elif factor == 4:
d_wdfmuxsel = 0
d_outmuxsel = 2
i_muxsel = 2
i_highrate_wdf1 = factor / 2 - 1
i_highrate_wdf2 = 0
elif 8 <= factor <= 64:
d_wdfmuxsel = 1
d_outmuxsel = 2
d_cic1_dec = factor / 4
d_cic1_bitshift = 12 - math.log(d_cic1_dec**3, 2)
i_muxsel = 3
i_ratechange_cic1 = factor / 4
i_interprate_cic1 = 0
i_bitshift_cic1 = math.log(i_ratechange_cic1**2, 2)
i_highrate_wdf1 = factor / 2 - 1
i_highrate_wdf2 = factor / 4 - 1
else: # 128 <= factor <= 1024
d_wdfmuxsel = 2
d_outmuxsel = 2
d_cic1_dec = 16
d_cic1_bitshift = 0
d_cic2_dec = factor / 64
d_cic2_bitshift = math.log(d_cic2_dec**3, 2)
i_muxsel = 4
i_ratechange_cic2 = factor / 64
i_interprate_cic2 = 0
i_bitshift_cic2 = math.log(i_ratechange_cic2**2, 2)
i_ratechange_cic1 = 16
i_bitshift_cic1 = 8
i_interprate_cic1 = i_ratechange_cic2 - 1
i_highrate_wdf1 = factor / 2 - 1
i_highrate_wdf2 = factor / 4 - 1
self._instr._accessor_set(self.regbase + self.REG_DECIMATION,
to_reg_unsigned(0, 2), d_wdfmuxsel)
self._instr._accessor_set(self.regbase + self.REG_DECIMATION,
to_reg_unsigned(2, 2), d_outmuxsel)
self._instr._accessor_set(self.regbase + self.REG_DECIMATION,
to_reg_unsigned(4, 4), d_cic1_bitshift)
self._instr._accessor_set(self.regbase + self.REG_DECIMATION,
to_reg_unsigned(8, 4), d_cic2_bitshift)
self._instr._accessor_set(self.regbase + self.REG_DECIMATION,
to_reg_unsigned(12, 5), d_cic1_dec)
self._instr._accessor_set(self.regbase + self.REG_DECIMATION,
to_reg_unsigned(17, 5), d_cic2_dec)
self._instr._accessor_set(self.regbase + self.REG_INTERP_CTRL,
to_reg_unsigned(0, 3), i_muxsel)
self._instr._accessor_set(self.regbase + self.REG_INTERP_WDFRATES,
to_reg_unsigned(0, 16), i_highrate_wdf1)
self._instr._accessor_set(self.regbase + self.REG_INTERP_WDFRATES,
to_reg_unsigned(16, 16), i_highrate_wdf2)
self._instr._accessor_set(self.regbase + self.REG_INTERP_CTRL,
to_reg_unsigned(3, 5), i_ratechange_cic1)
self._instr._accessor_set(self.regbase + self.REG_INTERP_CTRL,
to_reg_unsigned(8, 5), i_ratechange_cic2)
self._instr._accessor_set(self.regbase + self.REG_INTERP_CICRATES,
to_reg_unsigned(0, 16), i_interprate_cic1)
self._instr._accessor_set(self.regbase + self.REG_INTERP_CICRATES,
to_reg_unsigned(16, 16), i_interprate_cic2)
self._instr._accessor_set(self.regbase + self.REG_INTERP_CTRL,
to_reg_unsigned(13, 4), i_bitshift_cic1)
self._instr._accessor_set(self.regbase + self.REG_INTERP_CTRL,
to_reg_unsigned(17, 4), i_bitshift_cic2)
(REG_PID_CH0_OFFSET1,
to_reg_signed(16, 16, xform=lambda obj, x: x / obj._dac_gains()[0]),
from_reg_signed(16, 16, xform=lambda obj, x: x * obj._dac_gains()[0])),
'ch1_pid2_out_offset':
(REG_PID_CH0_OFFSET2,
to_reg_signed(16, 16, xform=lambda obj, x: x / obj._dac_gains()[0]),
from_reg_signed(16, 16, xform=lambda obj, x: x * obj._dac_gains()[0])),
'ch1_pid1_pidgain': (REG_PID_CH0_PIDGAIN1,
to_reg_signed(0, 32, xform=lambda obj, x: x),
from_reg_signed(0, 32, xform=lambda obj, x: x)),
'ch1_pid2_pidgain': (REG_PID_CH0_PIDGAIN2,
to_reg_signed(0, 32, xform=lambda obj, x: x),
from_reg_signed(0, 32, xform=lambda obj, x: x)),
'ch1_pid1_int_i_gain': (REG_PID_CH0_INT_IGAIN1,
to_reg_unsigned(0,
24,
xform=lambda obj, x: x *
(2.0**24 - 1)),
from_reg_unsigned(0,
24,
xform=lambda obj, x: x /
(2.0**24 - 1))),
# TODO: This concerns me, not sure if its writing to the registers as
# expected
'ch1_pid2_int_i_gain': ((REG_PID_CH0_INT_IGAIN2_MSB,
REG_PID_CH0_INT_IGAIN2_LSB),
to_reg_unsigned(24,
24,
xform=lambda obj, x: x *
(2.0**24 - 1)),
from_reg_unsigned(24,
def _on_reg_sync(self):
super(IIRFilterBox, self)._on_reg_sync()
# Update local variables with device variables
self._sync_control_matrix_regs()
self._sync_gains_offsets_regs()
# TODO: Sync previous IIR filter coefficients to local coefficient
# variables
# self.filter_ch1 = ...
# self.filter_ch2 = ...
_iir_reg_handlers = {
'mon1_source':
(REG_MONSELECT, to_reg_unsigned(0, 3), from_reg_unsigned(0, 3)),
'mon2_source': (REG_MONSELECT, to_reg_unsigned(3,
3), from_reg_unsigned(3,
3)),
'input_en1': (REG_ENABLE, to_reg_unsigned(0, 1), from_reg_unsigned(0, 1)),
'input_en2': (REG_ENABLE, to_reg_unsigned(1, 1), from_reg_unsigned(1, 1)),
'output_en1': (REG_ENABLE, to_reg_unsigned(2, 1), from_reg_unsigned(2, 1)),
'output_en2': (REG_ENABLE, to_reg_unsigned(3, 1), from_reg_unsigned(3, 1)),
'matrixscale_ch1_ch1':
(REG_CH0_CH0GAIN,
to_reg_signed(0,
16,
xform=lambda obj, x: int(
round(x * (_ADC_DEFAULT_CALIBRATION /
(10.0 if obj.get_frontend(1)[1] else 1.0)) *
obj._adc_gains()[0] * 2.0**10))),
def gain(self, value):
r = self.reg_base + PID._REG_GAIN
self._instr._accessor_set(r, to_reg_unsigned(0, 32), value)
