def construct(s):
s.foo = Wire(Bits32)
s.bar = Wire(Bits4)
@s.update
def upblk():
s.foo = 42
s.bar = Bits4(0)
def construct(s, nbits=0):
s.in_ = InPort(mk_bits(nbits))
s.out = OutPort(mk_bits(nbits))
s.w = Wire(mk_bits(nbits))
connect(s.w, s.out)
s.inner = Foo(32)(in_=s.in_, out=s.w)
def construct(s):
s.foo = [Wire(Bits32) for _ in range(5)]
@s.update
def upblk():
for i in range(5):
s.foo[i] = Bits32(0)
def construct(s):
s.struct = Wire(B)
@s.update
def upblk():
s.struct.foo = 0
s.struct.bar = Bits16(42)
def construct(s):
s.in_ = Wire(Bits4)
s.out = OutPort(Bits4)
@s.update
def upblk():
for s.in_ in range(4):
s.out = Bits4(1)
def construct(s):
s.wire = [Wire(Bits32) for _ in range(5)]
s.bar = OutPort(Bits32)
connect(s.bar, s.wire[1])
@s.update
def upblk():
for i in range(5):
s.wire[i] = Bits32(0)
def construct(s, init=0):
s.en = Wire(32)
@update_ff
def ff():
if s.reset:
s.en <<= init
else:
s.en <<= s.en ^ 1
def construct(s, nbits=1):
s.in_ = InPort(nbits)
s.out = OutPort(nbits)
s.w = Wire(nbits)
connect(s.w, s.out)
s.inner = Foo(32)
s.inner.in_ //= s.in_
s.inner.out //= s.w
def construct(s, nbits=1):
s.in_ = InPort(nbits)
s.out = OutPort(nbits)
s.w = Wire(nbits)
connect(s.w, s.out)
s.inner = Real_shamt(5)
s.inner.in_ //= s.in_
s.inner.out //= s.w
def construct( s ):
s.in_ = InPort( Bits32 )
s.wire = Wire( Bits32 )
s.out = OutPort( Bits32 )
connect( s.in_, s.wire )
@s.update
def out():
s.out = s.wire + 444
def construct( s ):
s.in_ = InPort( strc )
s.out_foo = OutPort( Bits32 )
s.out_bar = OutPort( Bits32 )
s.out_sum = OutPort( Bits16 )
s.sum = [ Wire( Bits16 ) for _ in range(3) ]
@s.update
def upblk():
for i in range(3):
s.sum[i] = s.in_.packed_array[i][0] + s.in_.packed_array[i][1]
s.out_sum = s.sum[0] + s.sum[1] + s.sum[2]
connect( s.out_foo, s.in_.foo )
connect( s.out_bar, s.in_.inner.bar )
def construct( s, nbits=0 ):
s.in_ = InPort ( mk_bits(nbits) )
s.out = OutPort( mk_bits(nbits) )
s.w = Wire( mk_bits(nbits) )
connect( s.w, s.out )
@s.update
def up_in():
s.inner.in_ = s.in_
@s.update
def up_out():
s.w = s.inner.out
s.inner = Real_shamt( 5 )#( in_ = s.in_, out = s.w )
def construct( s ):
s.in_ = InPort( Bits32 )
s.out = OutPort( Bits32 )
s.out2 = OutPort( Bits32 )
@s.update
def up_out():
s.out = Bits32(0)
s.wire = Wire(Bits32)
@s.update_ff
def up_ff():
s.wire <<= s.wire + 1
@s.update
def up_out2():
s.out2 = Bits32(0)
def construct( s, nbits=0 ):
s.in_ = InPort ( mk_bits(nbits) )
s.out = OutPort( mk_bits(nbits) )
s.w = Wire( mk_bits(nbits) )
connect( s.w, s.out )
@s.func
def assign_in( x ):
s.inner.in_ = x
@s.update
def up_in():
assign_in( s.in_ )
@s.func
def read_out():
s.w = s.inner.out
@s.update
def up_out():
read_out()
s.inner = Real_shamt( 5 )#( in_ = s.in_, out = s.w )
def construct(s):
s.out = [OutPort(Bits32) for _ in range(5)]
s.wire_ = [Wire(Bits32) for _ in range(5)]
for i in range(5):
connect(s.wire_[i], s.out[i])
connect(s.wire_[i], i)
def construct(s):
s.in_ = InPort(Bits32)
s.wire_ = Wire(Bits32)
s.out = OutPort(Bits32)
connect(s.in_, s.wire_)
connect(s.wire_, s.out)
def construct(s, T1, T2, T3, T4, T5, T6, T7):
s.in_ = InPort(Bits32)
s.wire_ = Wire(Bits32)
s.out = OutPort(Bits32)
connect(s.in_, s.wire_)
connect(s.wire_, s.out)
def construct(s, *args, **kwargs):
# Set up the VCD file name
verilator_vcd_file = ""
if 1:
if True:
verilator_vcd_file = "SPI_pymtl2.SPIStacks.FPUStack.test.FPUStack_test__test_stack_8bit_basic_0x0_top_fpu_stack_fpu_retimed.verilator1.vcd"
else:
verilator_vcd_file = "FPURetimed_noparam.verilator1.vcd"
# Convert string to `bytes` which is required by CFFI on python 3
verilator_vcd_file = verilator_vcd_file.encode('ascii')
# Construct the model
s._ffi_m = s._ffi_inst.create_model(
s.ffi.new("char[]", verilator_vcd_file))
# Buffer for line tracing
s._line_trace_str = s.ffi.new('char[512]')
s._convert_string = s.ffi.string
# Use non-attribute varialbe to reduce CPython bytecode count
_ffi_m = s._ffi_m
_ffi_inst_comb_eval = s._ffi_inst.comb_eval
_ffi_inst_seq_eval = s._ffi_inst.seq_eval
# declare the port interface
s.req_msg = InPort(Bits128)
s.req_rdy = OutPort(Bits1)
s.req_val = InPort(Bits1)
s.resp_msg = OutPort(Bits128)
s.resp_rdy = InPort(Bits1)
s.resp_val = OutPort(Bits1)
# update blocks that converts ffi interface to/from pymtl ports
s.s_DOT_req_msg = Wire(Bits128)
@update
def isignal_s_DOT_req_msg():
s.s_DOT_req_msg @= s.req_msg
s.s_DOT_req_val = Wire(Bits1)
@update
def isignal_s_DOT_req_val():
s.s_DOT_req_val @= s.req_val
s.s_DOT_resp_rdy = Wire(Bits1)
@update
def isignal_s_DOT_resp_rdy():
s.s_DOT_resp_rdy @= s.resp_rdy
s.s_DOT_req_rdy = Wire(Bits1)
@update
def osignal_s_DOT_req_rdy():
s.req_rdy @= s.s_DOT_req_rdy
s.s_DOT_resp_msg = Wire(Bits128)
@update
def osignal_s_DOT_resp_msg():
s.resp_msg @= s.s_DOT_resp_msg
s.s_DOT_resp_val = Wire(Bits1)
@update
def osignal_s_DOT_resp_val():
s.resp_val @= s.s_DOT_resp_val
@update
def comb_upblk():
# Set inputs
x = _ffi_m.req_msg
x[0] = int(s.s_DOT_req_msg[0:32])
x[1] = int(s.s_DOT_req_msg[32:64])
x[2] = int(s.s_DOT_req_msg[64:96])
x[3] = int(s.s_DOT_req_msg[96:128])
_ffi_m.req_val[0] = int(s.s_DOT_req_val)
_ffi_m.resp_rdy[0] = int(s.s_DOT_resp_rdy)
_ffi_inst_comb_eval(_ffi_m)
# Write all outputs
s.s_DOT_req_rdy @= _ffi_m.req_rdy[0]
x = _ffi_m.resp_msg
s.s_DOT_resp_msg[0:32] @= x[0]
s.s_DOT_resp_msg[32:64] @= x[1]
s.s_DOT_resp_msg[64:96] @= x[2]
s.s_DOT_resp_msg[96:128] @= x[3]
s.s_DOT_resp_val @= _ffi_m.resp_val[0]
@update_ff
def seq_upblk():
# seq_eval will automatically tick clock in C land
_ffi_inst_seq_eval(_ffi_m)
def construct(s, *args, **kwargs):
# Set up the VCD file name
verilator_vcd_file = ""
if 1:
if True:
verilator_vcd_file = "SPI_pymtl2.SPIStacks.FPUStack.test.FPUStack_test__test_stack_8bit_basic_0x0_top_fpu_stack_spi_stack_spi_loopback.verilator1.vcd"
else:
verilator_vcd_file = "SPILoopback__pack_size_128.verilator1.vcd"
# Convert string to `bytes` which is required by CFFI on python 3
verilator_vcd_file = verilator_vcd_file.encode('ascii')
# Construct the model
s._ffi_m = s._ffi_inst.create_model(
s.ffi.new("char[]", verilator_vcd_file))
# Buffer for line tracing
s._line_trace_str = s.ffi.new('char[512]')
s._convert_string = s.ffi.string
# Use non-attribute varialbe to reduce CPython bytecode count
_ffi_m = s._ffi_m
_ffi_inst_comb_eval = s._ffi_inst.comb_eval
_ffi_inst_seq_eval = s._ffi_inst.seq_eval
# declare the port interface
s.from_device = InPort(Bits128)
s.from_master = InPort(Bits128)
s.loop_en = InPort(Bits1)
s.serve = InPort(Bits1)
s.to_device = OutPort(Bits128)
s.to_master = OutPort(Bits128)
# update blocks that converts ffi interface to/from pymtl ports
s.s_DOT_from_device = Wire(Bits128)
@update
def isignal_s_DOT_from_device():
s.s_DOT_from_device @= s.from_device
s.s_DOT_from_master = Wire(Bits128)
@update
def isignal_s_DOT_from_master():
s.s_DOT_from_master @= s.from_master
s.s_DOT_loop_en = Wire(Bits1)
@update
def isignal_s_DOT_loop_en():
s.s_DOT_loop_en @= s.loop_en
s.s_DOT_serve = Wire(Bits1)
@update
def isignal_s_DOT_serve():
s.s_DOT_serve @= s.serve
s.s_DOT_to_device = Wire(Bits128)
@update
def osignal_s_DOT_to_device():
s.to_device @= s.s_DOT_to_device
s.s_DOT_to_master = Wire(Bits128)
@update
def osignal_s_DOT_to_master():
s.to_master @= s.s_DOT_to_master
@update
def comb_upblk():
# Set inputs
x = _ffi_m.from_device
x[0] = int(s.s_DOT_from_device[0:32])
x[1] = int(s.s_DOT_from_device[32:64])
x[2] = int(s.s_DOT_from_device[64:96])
x[3] = int(s.s_DOT_from_device[96:128])
x = _ffi_m.from_master
x[0] = int(s.s_DOT_from_master[0:32])
x[1] = int(s.s_DOT_from_master[32:64])
x[2] = int(s.s_DOT_from_master[64:96])
x[3] = int(s.s_DOT_from_master[96:128])
_ffi_m.loop_en[0] = int(s.s_DOT_loop_en)
_ffi_m.serve[0] = int(s.s_DOT_serve)
_ffi_inst_comb_eval(_ffi_m)
# Write all outputs
x = _ffi_m.to_device
s.s_DOT_to_device[0:32] @= x[0]
s.s_DOT_to_device[32:64] @= x[1]
s.s_DOT_to_device[64:96] @= x[2]
s.s_DOT_to_device[96:128] @= x[3]
x = _ffi_m.to_master
s.s_DOT_to_master[0:32] @= x[0]
s.s_DOT_to_master[32:64] @= x[1]
s.s_DOT_to_master[64:96] @= x[2]
s.s_DOT_to_master[96:128] @= x[3]
@update_ff
def seq_upblk():
# seq_eval will automatically tick clock in C land
_ffi_inst_seq_eval(_ffi_m)
def construct(s, *args, **kwargs):
# Set up the VCD file name
verilator_vcd_file = ""
if 0:
if False:
verilator_vcd_file = ".vcd"
else:
verilator_vcd_file = "Ix.verilator1.vcd"
# Convert string to `bytes` which is required by CFFI on python 3
verilator_vcd_file = verilator_vcd_file.encode('ascii')
# Construct the model
s._ffi_m = s._ffi_inst.create_model(
s.ffi.new("char[]", verilator_vcd_file))
# Buffer for line tracing
s._line_trace_str = s.ffi.new('char[512]')
s._convert_string = s.ffi.string
# Use non-attribute varialbe to reduce CPython bytecode count
_ffi_m = s._ffi_m
_ffi_inst = s._ffi_inst
# declare the port interface
s.image_in = [InPort(Bits32) for _ in range(15)]
s.image_out = [OutPort(Bits32) for _ in range(9)]
# update blocks that converts ffi interface to/from pymtl ports
s.s_DOT_image_in_LB_0_RB_ = Wire(Bits32)
@s.update
def isignal_s_DOT_image_in_LB_0_RB_():
s.s_DOT_image_in_LB_0_RB_ = s.image_in[0]
s.s_DOT_image_in_LB_1_RB_ = Wire(Bits32)
@s.update
def isignal_s_DOT_image_in_LB_1_RB_():
s.s_DOT_image_in_LB_1_RB_ = s.image_in[1]
s.s_DOT_image_in_LB_2_RB_ = Wire(Bits32)
@s.update
def isignal_s_DOT_image_in_LB_2_RB_():
s.s_DOT_image_in_LB_2_RB_ = s.image_in[2]
s.s_DOT_image_in_LB_3_RB_ = Wire(Bits32)
@s.update
def isignal_s_DOT_image_in_LB_3_RB_():
s.s_DOT_image_in_LB_3_RB_ = s.image_in[3]
s.s_DOT_image_in_LB_4_RB_ = Wire(Bits32)
@s.update
def isignal_s_DOT_image_in_LB_4_RB_():
s.s_DOT_image_in_LB_4_RB_ = s.image_in[4]
s.s_DOT_image_in_LB_5_RB_ = Wire(Bits32)
@s.update
def isignal_s_DOT_image_in_LB_5_RB_():
s.s_DOT_image_in_LB_5_RB_ = s.image_in[5]
s.s_DOT_image_in_LB_6_RB_ = Wire(Bits32)
@s.update
def isignal_s_DOT_image_in_LB_6_RB_():
s.s_DOT_image_in_LB_6_RB_ = s.image_in[6]
s.s_DOT_image_in_LB_7_RB_ = Wire(Bits32)
@s.update
def isignal_s_DOT_image_in_LB_7_RB_():
s.s_DOT_image_in_LB_7_RB_ = s.image_in[7]
s.s_DOT_image_in_LB_8_RB_ = Wire(Bits32)
@s.update
def isignal_s_DOT_image_in_LB_8_RB_():
s.s_DOT_image_in_LB_8_RB_ = s.image_in[8]
s.s_DOT_image_in_LB_9_RB_ = Wire(Bits32)
@s.update
def isignal_s_DOT_image_in_LB_9_RB_():
s.s_DOT_image_in_LB_9_RB_ = s.image_in[9]
s.s_DOT_image_in_LB_10_RB_ = Wire(Bits32)
@s.update
def isignal_s_DOT_image_in_LB_10_RB_():
s.s_DOT_image_in_LB_10_RB_ = s.image_in[10]
s.s_DOT_image_in_LB_11_RB_ = Wire(Bits32)
@s.update
def isignal_s_DOT_image_in_LB_11_RB_():
s.s_DOT_image_in_LB_11_RB_ = s.image_in[11]
s.s_DOT_image_in_LB_12_RB_ = Wire(Bits32)
@s.update
def isignal_s_DOT_image_in_LB_12_RB_():
s.s_DOT_image_in_LB_12_RB_ = s.image_in[12]
s.s_DOT_image_in_LB_13_RB_ = Wire(Bits32)
@s.update
def isignal_s_DOT_image_in_LB_13_RB_():
s.s_DOT_image_in_LB_13_RB_ = s.image_in[13]
s.s_DOT_image_in_LB_14_RB_ = Wire(Bits32)
@s.update
def isignal_s_DOT_image_in_LB_14_RB_():
s.s_DOT_image_in_LB_14_RB_ = s.image_in[14]
s.s_DOT_image_out_LB_0_RB_ = Wire(Bits32)
@s.update
def osignal_s_DOT_image_out_LB_0_RB_():
s.image_out[0] = s.s_DOT_image_out_LB_0_RB_
s.s_DOT_image_out_LB_1_RB_ = Wire(Bits32)
@s.update
def osignal_s_DOT_image_out_LB_1_RB_():
s.image_out[1] = s.s_DOT_image_out_LB_1_RB_
s.s_DOT_image_out_LB_2_RB_ = Wire(Bits32)
@s.update
def osignal_s_DOT_image_out_LB_2_RB_():
s.image_out[2] = s.s_DOT_image_out_LB_2_RB_
s.s_DOT_image_out_LB_3_RB_ = Wire(Bits32)
@s.update
def osignal_s_DOT_image_out_LB_3_RB_():
s.image_out[3] = s.s_DOT_image_out_LB_3_RB_
s.s_DOT_image_out_LB_4_RB_ = Wire(Bits32)
@s.update
def osignal_s_DOT_image_out_LB_4_RB_():
s.image_out[4] = s.s_DOT_image_out_LB_4_RB_
s.s_DOT_image_out_LB_5_RB_ = Wire(Bits32)
@s.update
def osignal_s_DOT_image_out_LB_5_RB_():
s.image_out[5] = s.s_DOT_image_out_LB_5_RB_
s.s_DOT_image_out_LB_6_RB_ = Wire(Bits32)
@s.update
def osignal_s_DOT_image_out_LB_6_RB_():
s.image_out[6] = s.s_DOT_image_out_LB_6_RB_
s.s_DOT_image_out_LB_7_RB_ = Wire(Bits32)
@s.update
def osignal_s_DOT_image_out_LB_7_RB_():
s.image_out[7] = s.s_DOT_image_out_LB_7_RB_
s.s_DOT_image_out_LB_8_RB_ = Wire(Bits32)
@s.update
def osignal_s_DOT_image_out_LB_8_RB_():
s.image_out[8] = s.s_DOT_image_out_LB_8_RB_
@s.update
def comb_upblk():
# Set inputs
_ffi_m.image_in[0][0] = int(s.s_DOT_image_in_LB_0_RB_)
_ffi_m.image_in[1][0] = int(s.s_DOT_image_in_LB_1_RB_)
_ffi_m.image_in[2][0] = int(s.s_DOT_image_in_LB_2_RB_)
_ffi_m.image_in[3][0] = int(s.s_DOT_image_in_LB_3_RB_)
_ffi_m.image_in[4][0] = int(s.s_DOT_image_in_LB_4_RB_)
_ffi_m.image_in[5][0] = int(s.s_DOT_image_in_LB_5_RB_)
_ffi_m.image_in[6][0] = int(s.s_DOT_image_in_LB_6_RB_)
_ffi_m.image_in[7][0] = int(s.s_DOT_image_in_LB_7_RB_)
_ffi_m.image_in[8][0] = int(s.s_DOT_image_in_LB_8_RB_)
_ffi_m.image_in[9][0] = int(s.s_DOT_image_in_LB_9_RB_)
_ffi_m.image_in[10][0] = int(s.s_DOT_image_in_LB_10_RB_)
_ffi_m.image_in[11][0] = int(s.s_DOT_image_in_LB_11_RB_)
_ffi_m.image_in[12][0] = int(s.s_DOT_image_in_LB_12_RB_)
_ffi_m.image_in[13][0] = int(s.s_DOT_image_in_LB_13_RB_)
_ffi_m.image_in[14][0] = int(s.s_DOT_image_in_LB_14_RB_)
_ffi_inst.eval(_ffi_m)
# Write all outputs
s.s_DOT_image_out_LB_0_RB_ = Bits32(_ffi_m.image_out[0][0])
s.s_DOT_image_out_LB_1_RB_ = Bits32(_ffi_m.image_out[1][0])
s.s_DOT_image_out_LB_2_RB_ = Bits32(_ffi_m.image_out[2][0])
s.s_DOT_image_out_LB_3_RB_ = Bits32(_ffi_m.image_out[3][0])
s.s_DOT_image_out_LB_4_RB_ = Bits32(_ffi_m.image_out[4][0])
s.s_DOT_image_out_LB_5_RB_ = Bits32(_ffi_m.image_out[5][0])
s.s_DOT_image_out_LB_6_RB_ = Bits32(_ffi_m.image_out[6][0])
s.s_DOT_image_out_LB_7_RB_ = Bits32(_ffi_m.image_out[7][0])
s.s_DOT_image_out_LB_8_RB_ = Bits32(_ffi_m.image_out[8][0])
if 0:
@s.update_ff
def seq_upblk():
# Advance the clock
_ffi_m.inv_clk[0] = 0
_ffi_inst.eval(_ffi_m)
_ffi_m.inv_clk[0] = 1
_ffi_inst.eval(_ffi_m)