def rtlir_tr_subcomp_port_decl(s, m, c_id, c_rtype, c_array_type, port_id,
port_rtype, port_dtype, port_array_type):
port_def_rtype = rt.Wire(port_dtype["raw_dtype"])
return {
'def':
s.rtlir_tr_wire_decl('{c_id}__' + port_id, port_def_rtype,
port_array_type, port_dtype),
'decl':
'.{port_id}( {{c_id}}__{port_id} )'.format(**locals())
}
def rtlir_tr_subcomp_ifc_port_decl(s, m, c_id, c_rtype, c_array_type,
ifc_id, ifc_rtype, ifc_array_type,
port_id, port_rtype, port_array_type):
assert isinstance( port_rtype, rt.Port ), \
"SystemVerilog backend does not support nested interface {} yet!".format(
port_id )
port_dtype = s.rtlir_data_type_translation(m, port_rtype.get_dtype())
port_def_rtype = rt.Wire(port_dtype["raw_dtype"])
return {
'def' : s.rtlir_tr_wire_decl('{c_id}__{ifc_id}__'+port_id, port_def_rtype,
port_array_type, port_dtype),
'decl' : '.{{ifc_id}}__{port_id}( {{c_id}}__{{ifc_id}}__{port_id} )'. \
format(**locals())
}
def rtlir_tr_behavioral_tmpvar( s, id_, upblk_id, dtype ):
return s.rtlir_tr_wire_decl(
"__tmpvar__"+upblk_id+'_'+id_, rt.Wire(dtype['raw_dtype']),
s.rtlir_tr_unpacked_array_type(None), dtype )
