def construct(s, MsgType, src_msgs, sink_msgs):
s.src = TestSrcCL(MsgType, src_msgs)
s.src_q = BypassQueueRTL(MsgType, num_entries=1)
s.dut = OutputUnitRTL(MsgType)
s.sink = TestSinkCL(MsgType, sink_msgs)
# Connections
s.src.send //= s.src_q.enq
s.src_q.deq //= s.dut.get
s.dut.send //= s.sink.recv
def construct( s, Header, num_outports, pkts ):
PhitType = mk_bits( Header.nbits )
sink_pkts = route_fl( Header, num_outports, pkts )
s.src = TestSource( Header, pkts )
s.src_q = BypassQueueRTL( PhitType, num_entries=1 )
s.dut = XbarRouteUnitMflitRTL( Header, num_outports )
s.sink = [ TestSink( Header, sink_pkts[i] ) for i in range( num_outports ) ]
s.src.send //= s.src_q.enq
s.src_q.deq //= s.dut.get
for i in range( num_outports ):
s.sink[i].recv.msg //= s.dut.give[i].ret
s.sink[i].recv.en //= lambda: s.dut.give[i].rdy & s.sink[i].recv.rdy
s.dut.give[i].en //= lambda: s.dut.give[i].rdy & s.sink[i].recv.rdy
def construct( s, PositionType, pkts, x, y ):
PhitType = Bits64
sink_pkts = route_unit_fl( pkts, x, y, )
s.src = TestSource( PitonNoCHeader, pkts )
s.src_q = BypassQueueRTL( PhitType, num_entries=1 )
s.dut = PitonRouteUnit( PositionType )
s.sink = [ TestSink( PitonNoCHeader, sink_pkts[i] ) for i in range(5) ]
s.src.send //= s.src_q.enq
s.src_q.deq //= s.dut.get
s.dut.pos //= PositionType( x, y )
for i in range(5):
s.sink[i].recv.msg //= s.dut.give[i].ret
s.sink[i].recv.en //= lambda: s.dut.give[i].rdy & s.sink[i].recv.rdy
s.dut.give[i].en //= lambda: s.dut.give[i].rdy & s.sink[i].recv.rdy
def construct(s, HeaderFormat, PositionType, pkts, x, y):
PhitType = mk_bits(HeaderFormat.nbits)
sink_pkts = route_unit_fl(HeaderFormat, pkts, x, y)
s.src = TestSource(HeaderFormat, pkts)
s.src_q = BypassQueueRTL(PhitType, num_entries=1)
s.dut = MeshRouteUnitRTLMflitXY(HeaderFormat, PositionType)
s.sink = [TestSink(HeaderFormat, sink_pkts[i]) for i in range(5)]
s.src.send //= s.src_q.enq
s.src_q.deq //= s.dut.get
s.dut.pos //= PositionType(x, y)
for i in range(5):
s.sink[i].recv.msg //= s.dut.give[i].ret
s.sink[i].recv.en //= lambda: s.dut.give[i].rdy & s.sink[i
].recv.rdy
s.dut.give[i].en //= lambda: s.dut.give[i].rdy & s.sink[i].recv.rdy
def construct(s, MsgType, vc=2, credit_line=1):
assert vc > 1
# Interface
s.recv = RecvIfcRTL(MsgType)
s.send = CreditSendIfcRTL(MsgType, vc)
s.MsgType = MsgType
s.vc = vc
# Components
CreditType = mk_bits(clog2(credit_line + 1))
# FIXME: use multiple buffers to avoid deadlock.
s.buffer = BypassQueueRTL(MsgType, num_entries=1)
s.credit = [Counter(CreditType, credit_line) for _ in range(vc)]
s.recv //= s.buffer.enq
s.buffer.deq.ret //= s.send.msg
@update
def up_credit_send():
s.send.en @= 0
s.buffer.deq.en @= 0
if s.buffer.deq.rdy:
for i in range(vc):
if (i == s.buffer.deq.ret.vc_id) & (s.credit[i].count > 0):
s.send.en @= 1
s.buffer.deq.en @= 1
@update
def up_counter_decr():
for i in range(vc):
s.credit[i].decr @= s.send.en & (i == s.send.msg.vc_id)
for i in range(vc):
s.credit[i].incr //= s.send.yum[i]
s.credit[i].load //= 0
s.credit[i].load_value //= 0
def construct( s, Type, src_msgs, sink_msgs, vc=2, credit_line=2 ):
s.src = TestSrcRTL( Type, src_msgs )
s.src_q = BypassQueueRTL( Type, num_entries=1 )
s.output_unit = OutputUnitCreditRTL( Type, vc=vc, credit_line=credit_line )
s.input_unit = InputUnitCreditRTL( Type, vc=vc, credit_line=credit_line )
s.switch_unit = SwitchUnitRTL( Type, num_inports=vc )
s.sink = TestNetSinkRTL( Type, sink_msgs )
s.src.send //= s.src_q.enq
s.src_q.deq //= s.output_unit.get
s.output_unit.send //= s.input_unit.recv
s.switch_unit.give.ret //= s.sink.recv.msg
for i in range( vc ):
s.input_unit.give[i] //= s.switch_unit.get[i]
@update
def up_sink_recv():
both_rdy = s.switch_unit.give.rdy & s.sink.recv.rdy
s.sink.recv.en @= both_rdy
s.switch_unit.give.en @= both_rdy
def construct( s ):
req_class, resp_class = mk_mem_msg( 8, 32, 32 )
# Proc/Mngr Interface
s.mngr2proc = RecvIfcRTL( Bits32 )
s.proc2mngr = SendIfcRTL( Bits32 )
# Instruction Memory Request/Response Interface
s.imem = MemMasterIfcRTL( req_class, resp_class )
# Data Memory Request/Response Interface
s.dmem = MemMasterIfcRTL( req_class, resp_class )
# Xcel Request/Response Interface
xreq_class, xresp_class = mk_xcel_msg( 5, 32 )
s.xcel = XcelMasterIfcRTL( xreq_class, xresp_class )
# val_W port used for counting commited insts.
s.commit_inst = OutPort( Bits1 )
# Bypass queues
s.imemreq_q = BypassQueue2RTL( req_class, 2 )
# We have to turn input receive interface into get interface
s.imemresp_q = BypassQueueRTL( resp_class, 1 )
s.dmemresp_q = BypassQueueRTL( resp_class, 1 )
s.mngr2proc_q = BypassQueueRTL( Bits32, 1 )
s.xcelresp_q = BypassQueueRTL( xresp_class, 1 )
# imem drop unit
s.imemresp_drop = m = DropUnitRTL( Bits32 )
m.in_.en //= s.imemresp_q.deq.en
m.in_.rdy //= s.imemresp_q.deq.rdy
m.in_.ret //= s.imemresp_q.deq.ret.data
# connect all the queues
s.imemreq_q.deq //= s.imem.req
s.imemresp_q.enq //= s.imem.resp
s.dmemresp_q.enq //= s.dmem.resp
s.mngr2proc_q.enq //= s.mngr2proc
s.xcelresp_q.enq //= s.xcel.resp
# Control
s.ctrl = m = ProcCtrl()
# imem port
m.imemresp_drop //= s.imemresp_drop.drop
m.imemreq_en //= s.imemreq_q.enq.en
m.imemreq_rdy //= s.imemreq_q.enq.rdy
m.imemresp_en //= s.imemresp_drop.out.en
m.imemresp_rdy //= s.imemresp_drop.out.rdy
# dmem port
m.dmemreq_en //= s.dmem.req.en
m.dmemreq_rdy //= s.dmem.req.rdy
m.dmemreq_type //= s.dmem.req.msg.type_
m.dmemresp_en //= s.dmemresp_q.deq.en
m.dmemresp_rdy //= s.dmemresp_q.deq.rdy
# xcel port
m.xcelreq_type //= s.xcel.req.msg.type_
m.xcelreq_en //= s.xcel.req.en
m.xcelreq_rdy //= s.xcel.req.rdy
m.xcelresp_en //= s.xcelresp_q.deq.en
m.xcelresp_rdy //= s.xcelresp_q.deq.rdy
# proc2mngr and mngr2proc
m.proc2mngr_en //= s.proc2mngr.en
m.proc2mngr_rdy //= s.proc2mngr.rdy
m.mngr2proc_en //= s.mngr2proc_q.deq.en
m.mngr2proc_rdy //= s.mngr2proc_q.deq.rdy
# commit inst for counting
m.commit_inst //= s.commit_inst
# Dpath
s.dpath = m = ProcDpath()
# imem ports
m.imemreq_addr //= s.imemreq_q.enq.msg.addr
m.imemresp_data //= s.imemresp_drop.out.ret
# dmem ports
m.dmemreq_addr //= s.dmem.req.msg.addr
m.dmemreq_data //= s.dmem.req.msg.data
m.dmemresp_data //= s.dmemresp_q.deq.ret.data
# xcel ports
m.xcelreq_addr //= s.xcel.req.msg.addr
m.xcelreq_data //= s.xcel.req.msg.data
m.xcelresp_data //= s.xcelresp_q.deq.ret.data
# mngr
m.mngr2proc_data //= s.mngr2proc_q.deq.ret
m.proc2mngr_data //= s.proc2mngr.msg
# Ctrl <-> Dpath
s.ctrl.reg_en_F //= s.dpath.reg_en_F
s.ctrl.pc_sel_F //= s.dpath.pc_sel_F
s.ctrl.reg_en_D //= s.dpath.reg_en_D
s.ctrl.op1_byp_sel_D //= s.dpath.op1_byp_sel_D
s.ctrl.op2_byp_sel_D //= s.dpath.op2_byp_sel_D
s.ctrl.op2_sel_D //= s.dpath.op2_sel_D
s.ctrl.imm_type_D //= s.dpath.imm_type_D
s.ctrl.reg_en_X //= s.dpath.reg_en_X
s.ctrl.alu_fn_X //= s.dpath.alu_fn_X
s.ctrl.reg_en_M //= s.dpath.reg_en_M
s.ctrl.wb_result_sel_M //= s.dpath.wb_result_sel_M
s.ctrl.reg_en_W //= s.dpath.reg_en_W
s.ctrl.rf_waddr_W //= s.dpath.rf_waddr_W
s.ctrl.rf_wen_W //= s.dpath.rf_wen_W
s.dpath.inst_D //= s.ctrl.inst_D
s.dpath.ne_X //= s.ctrl.ne_X