def test_random(data_nbits, num_entries, dump_vcd, test_verilog):
dut = SramRTL(data_nbits, num_entries)
config_model(dut, dump_vcd, test_verilog)
tvec = gen_rand_tvec(data_nbits, num_entries)
run_test_vector_sim(dut, tvec)
def test_direct_128x512(dump_vcd, test_verilog):
test_vectors = [
header_str,
# val, type, wben, idx, wdata, rdata
[1, 0, 0b0000, 0, 0x00000000, '?'],
[1, 0, 0b0000, 0, 0x00000000, '?'],
[1, 1, 0b1111, 0, 0x00000000, '?'],
[1, 0, 0b0000, 0, 0x00000000, '?'],
[1, 0, 0b0000, 0, 0x00000000, 0x00000000],
[1, 1, 0b0001, 0, 0xdeadbeef, 0x00000000],
[1, 0, 0b0000, 0, 0x00000000, '?'],
[1, 0, 0b0000, 0, 0x00000000, 0x000000ef],
[1, 1, 0b0110, 0, 0xabcdefab, 0x000000ef],
[1, 0, 0b0000, 0, 0x00000000, '?'],
[1, 0, 0b0000, 0, 0x00000000, 0x00cdefef],
[1, 1, 0b1011, 0, 0xff000000, 0x00cdefef],
[1, 0, 0b0000, 0, 0x00000000, '?'],
[1, 0, 0b0000, 0, 0x00000000, 0xffcd0000],
[1, 1, 0b1111, 0, 0xdeadbeef, 0xffcd0000],
[1, 0, 0b0000, 0, 0x00000000, '?'],
[1, 0, 0b0000, 0, 0x00000000, 0xdeadbeef],
[1, 1, 0b1111, 0, 0xffffffff, 0xdeadbeef],
[1, 0, 0b0000, 0, 0x00000000, '?'],
[1, 0, 0b0000, 0, 0x00000000, 0xffffffff],
[1, 0, 0b0000, 0x1ff, 0x00000000, 0xffffffff],
[1, 1, 0b1111, 0x1ff, 0xdeadbeef, '?'],
[1, 0, 0b1111, 0x1ff, 0xbbbbcccc, '?'],
[1, 0, 0b0000, 0x1ff, 0x00000000, 0xdeadbeef],
]
run_test_vector_sim(SramRTL(128, 512), test_vectors, dump_vcd,
test_verilog)
def test_random(dump_vcd, test_verilog):
nvectors = 100 #numer of the random vectors
side = 3
bits_type = mk_bits(32)
hd_str = ' '.join([f"image_in[{i}]" for i in range(side * (side + 2))])
hd_str += ' '
hd_str += ' '.join([f"image_out[{i}]*" for i in range(side * side)])
# Generate test vectors
tvectors = [hd_str]
for i in range(nvectors):
vector = []
# Add input data
for j in range(side * (side + 2)):
vector.append(bits_type(random.randint(0, 1024)))
# Add output data
for k in range(0, side):
for l in range(0, side):
vector.append(vector[l + k * (side + 2) + 2] -
vector[l + (side + 2) * k])
tvectors.append(vector)
run_test_vector_sim(IxVRTL(3), tvectors, dump_vcd, test_verilog)
def test_random(dump_vcd, test_verilog):
nvectors = 100 #numer of the random vectors
side = 3
bits_type = mk_bits(32)
width = side + 2
hd_str = ' '.join(
[f"current_frame[{i}]" for i in range((side + 2) * (side + 2))])
hd_str += ' '
hd_str += ' '.join(
[f"next_frame[{i}]" for i in range((side + 2) * (side + 2))])
hd_str += ' '
hd_str += ' '.join([f"out[{i}]*" for i in range(side * side)])
# Generate test vectors
tvectors = [hd_str]
for i in range(nvectors):
vector = []
# Add input data
for j in range((side + 2) * (side + 2)):
vector.append(bits_type(random.randint(0, 1024)))
for k in range((side + 2) * (side + 2)):
vector.append(bits_type(random.randint(0, 1024)))
# Add output data
for l in range(0, side):
for m in range(0, side):
#vector.append(vector[l]-vector[l+size*size])
vector.append(vector[width * width + (l + 1) * width + m + 1] -
vector[(l + 1) * width + m + 1])
tvectors.append(vector)
run_test_vector_sim(ItVRTL(3), tvectors, dump_vcd, test_verilog)
#def test_large_pos( dump_vcd, test_verilog ):
# #dut = IntMulVarLatCalcShamtRTL() #need to change the name
# dut = step()
# config_model( dut, dump_vcd, test_verilog )
# run_test_vector_sim( dut, [
# ('req_msg_a req_msg_b presum resp_msg* a_shift*'),
# [ 0x7fff0000, 0, 0x00000000, 0x00000000, 0xfffe0000 ],
# [ 0x7fff0001, 0, 0x00000011, 0x00000011, 0xfffe0002 ],
# [ 0x7fff0000, 1, 0x00001000, 0x7fff1000, 0xfffe0000 ],
# [ 0x4dff1000, 1, 0x00001100, 0x4dff2100, 0x9bfe2000 ],
# ] )
#def Ixcal(image_in,image_out,size):
# for i in range (0,size):
# for j in range(0,size):
# image_out.append(image_in[j+i*(size+2)+2]-image_in[j+(size+2)*i])
# return
#image_in=[0,1,7,3,0,5,6,7,8,8,4,2,9,6,3]
#image_out=[]
#Ixcal(image_in,image_out,3)
#for i in image_out:
# print(i)
def test_basic(dump_vcd, test_verilog):
dut = IntMulVarLatCalcShamtRTL()
config_model(dut, dump_vcd, test_verilog)
run_test_vector_sim(dut, [
('in_ out*'),
[0x10, 4],
])
def test_directed( dump_vcd, test_verilog ):
# 4 Bits16 ports
run_test_vector_sim( PassThroughV1RTL( 4, 16 ), [
"in_[0] in_[1] in_[2] in_[3] out[0]* out[1]* out[2]* out[3]*",
[ b16(0), b16(0), b16(0), b16(0), b16(0), b16(0), b16(0), b16(0) ],
[ b16(1), b16(0), b16(3), b16(3), b16(1), b16(0), b16(3), b16(3) ],
[ b16(-1), b16(42), b16(30), b16(25), b16(-1), b16(42), b16(30), b16(25) ],
[ b16(42), b16(-1), b16(20), b16(16), b16(42), b16(-1), b16(20), b16(16) ],
], dump_vcd, test_verilog )
def test_alu_xor(dump_vcd, test_verilog):
dut = AluRTL()
config_model(dut, dump_vcd, test_verilog)
run_test_vector_sim(dut, [
('in0 in1 fn out* ops_eq* ops_lt* ops_ltu*'
),
[0x00000000, 0x00000000, 7, 0x00000000, '?', '?', '?'],
[0x0ffaa660, 0x00012304, 7, 0x0ffb8564, '?', '?', '?'],
[0x00132050, 0xd6620040, 7, 0xd6712010, '?', '?', '?'],
[0xfff0a440, 0x00004450, 7, 0xfff0e010, '?', '?', '?'],
[0xfeeeeaa3, 0xf4650000, 7, 0x0a8beaa3, '?', '?', '?'],
])
def test_alu_nor(dump_vcd, test_verilog):
dut = AluRTL()
config_model(dut, dump_vcd, test_verilog)
run_test_vector_sim(dut, [
('in0 in1 fn out* ops_eq* ops_lt* ops_ltu*'
),
[0x00000000, 0x00000000, 8, 0xffffffff, '?', '?', '?'],
[0x0ffaa660, 0x00012304, 8, 0xf004589b, '?', '?', '?'],
[0x00132050, 0xd6620040, 8, 0x298cdfaf, '?', '?', '?'],
[0xfff0a440, 0x00004450, 8, 0x000f1baf, '?', '?', '?'],
[0xfeeeeaa3, 0xf4650000, 8, 0x0110155c, '?', '?', '?'],
])
def test_alu_fn_equality(dump_vcd, test_verilog):
dut = AluRTL()
config_model(dut, dump_vcd, test_verilog)
run_test_vector_sim(dut, [
('in0 in1 fn out* ops_eq* ops_lt* ops_ltu*'
),
[0x00000000, 0x00000000, 14, 0x00000000, 1, '?', '?'],
[0x0ffaa660, 0x00012304, 14, 0x00000000, 0, '?', '?'],
[0x00132050, 0xd6620040, 14, 0x00000000, 0, '?', '?'],
[0xfff0a440, 0x00004450, 14, 0x00000000, 0, '?', '?'],
[0xfeeeeaa3, 0xf4650000, 14, 0x00000000, 0, '?', '?'],
])
def test_32b_x_4b_mult( dump_vcd, test_verilog ):
th = TestHarness()
config_model( th, dump_vcd, test_verilog, [f'steps[{i}]' for i in range(4)] )
run_test_vector_sim( th, [
('a b result*'),
[ 0, 0, 0 ],
[ 2, 3, 6 ],
[ 4, 5, 20 ],
[ 3, 4, 12 ],
[ 10, 13, 130 ],
[ 8, 7, 56 ],
] )
def test_basic(dump_vcd, test_verilog):
#dut = IntMulVarLatCalcShamtRTL() #need to change the name
dut = IyVRTL(3)
config_model(dut, dump_vcd, test_verilog)
run_test_vector_sim(
dut,
[
#('req_msg_a req_msg_b presum resp_msg* a_shift*'),
('image_in[0] image_in[1] image_in[2] image_in[3] image_in[4] image_in[5] image_in[6] image_in[7] image_in[8] image_in[9] image_in[10] image_in[11] image_in[12] image_in[13] image_in[14] image_in[15] image_in[16] image_in[17] image_in[18] image_in[19] image_in[20] image_in[21] image_in[22] image_in[23] image_in[24] image_out[0]* image_out[1]* image_out[2]* image_out[3]* image_out[4]* image_out[5]* image_out[6]* image_out[7]* image_out[8]*'
),
[
b32(0),
b32(1),
b32(2),
b32(3),
b32(4),
b32(5),
b32(6),
b32(7),
b32(8),
b32(9),
b32(10),
b32(11),
b32(12),
b32(13),
b32(14),
b32(15),
b32(16),
b32(17),
b32(18),
b32(19),
b32(20),
b32(21),
b32(22),
b32(23),
b32(24),
b32(10),
b32(10),
b32(10),
b32(10),
b32(10),
b32(10),
b32(10),
b32(10),
b32(10)
],
#[b32(0), b32(1), b32(7), b32(3), b32(0), b32(5), b32(6), b32(7), b32(8), b32(8), b32(4), b32(2), b32(9), b32(6), b32(3), b32(6), b32(6), b32(1), b32(5), b32(4), b32(-3), b32(3), b32(-1), b32(-5)],
])
def test_multiple_ones(dump_vcd, test_verilog):
dut = IntMulVarLatCalcShamtRTL()
config_model(dut, dump_vcd, test_verilog)
run_test_vector_sim(dut, [
('in_ out*'),
[0x00000011, 1],
[0x00000012, 1],
[0x00000014, 2],
[0x00000018, 3],
[0x00000010, 4],
[0x00000010, 4],
])
def test_basic( dump_vcd, test_verilog ):
dut = IntMulNstageStepRTL()
config_model( dut, dump_vcd, test_verilog )
run_test_vector_sim( dut, [
('in_en in_a in_b in_result in_en* out_a* out_b* out_result*'),
[ 0, 0x00000000, 0x00000000, 0x00000000, 0, 0x00000000, 0x00000000, 0x00000000 ],
[ 1, 0x00000000, 0x00000000, 0x00000000, 1, 0x00000000, 0x00000000, 0x00000000 ],
[ 1, 0x10101010, 0x00000000, 0x00000000, 1, 0x20202020, 0x00000000, 0x00000000 ],
[ 1, 0x10101010, 0x00000001, 0x00000000, 1, 0x20202020, 0x00000000, 0x10101010 ],
[ 1, 0x10101010, 0x00000000, 0x00000001, 1, 0x20202020, 0x00000000, 0x00000001 ],
[ 1, 0x10101010, 0x00000001, 0x00000001, 1, 0x20202020, 0x00000000, 0x10101011 ],
] )
def test_basic(dump_vcd, test_verilog):
run_test_vector_sim(
SortUnitStructRTL(),
[
header_str,
# in in in in in out out out out out
# val [0] [1] [2] [3] val [0] [1] [2] [3]
[0, 0, 0, 0, 0, 0, x, x, x, x],
[1, 4, 2, 3, 1, 0, x, x, x, x],
[0, 0, 0, 0, 0, 0, x, x, x, x],
[0, 0, 0, 0, 0, 0, x, x, x, x],
[0, 0, 0, 0, 0, 1, 1, 2, 3, 4],
[0, 0, 0, 0, 0, 0, x, x, x, x],
],
dump_vcd,
test_verilog)
def test_alu_sll(dump_vcd, test_verilog):
dut = AluRTL()
config_model(dut, dump_vcd, test_verilog)
run_test_vector_sim(dut, [
('in0 in1 fn out* ops_eq* ops_lt* ops_ltu*'
),
[0x00000000, 0x00000000, 2, 0x00000000, '?', '?', '?'],
[0x05050505, 0x00000001, 2, 0x0a0a0a0a, '?', '?', '?'],
[0x05050505, 0x00000002, 2, 0x14141414, '?', '?', '?'],
[0x05050505, 0x00000004, 2, 0x50505050, '?', '?', '?'],
[0x50505050, 0x00000008, 2, 0x50505000, '?', '?', '?'],
[0x50505050, 0x0000000f, 2, 0x28280000, '?', '?', '?'],
[0x50505050, 0x00000010, 2, 0x50500000, '?', '?', '?'],
[0x50505050, 0x0000001f, 2, 0x00000000, '?', '?', '?'],
])
def test_alu_srl(dump_vcd, test_verilog):
dut = AluRTL()
config_model(dut, dump_vcd, test_verilog)
run_test_vector_sim(dut, [
('in0 in1 fn out* ops_eq* ops_lt* ops_ltu*'
),
[0x00000000, 0x00000000, 9, 0x00000000, '?', '?', '?'],
[0x05050505, 0x00000001, 9, 0x02828282, '?', '?', '?'],
[0x05050505, 0x00000002, 9, 0x01414141, '?', '?', '?'],
[0x05050505, 0x00000004, 9, 0x00505050, '?', '?', '?'],
[0x50505050, 0x00000008, 9, 0x00505050, '?', '?', '?'],
[0x50505050, 0x0000000f, 9, 0x0000a0a0, '?', '?', '?'],
[0x50505050, 0x00000010, 9, 0x00005050, '?', '?', '?'],
[0x50505050, 0x0000001f, 9, 0x00000000, '?', '?', '?'],
])
def test_random_neg_pos_large( dump_vcd, test_verilog ):
nvectors = 100 #numer of the random vectors
side = 3
bits_type = mk_bits(32)
width =side+2
hd_str = ' '.join( [ f"en"])
hd_str += ' '
hd_str += ' '.join( [ f"current_frame[{i}]" for i in range(width*width) ] )
hd_str += ' '
hd_str += ' '.join( [ f"next_frame[{i}]" for i in range(width*width) ] )
hd_str += ' '
hd_str += ' '.join( [ f"Ix[{i}]*" for i in range(side*side) ] )
hd_str += ' '
hd_str += ' '.join( [ f"Iy[{i}]*" for i in range(side*side) ] )
hd_str += ' '
hd_str += ' '.join( [ f"It[{i}]*" for i in range(side*side) ] )
hd_str += ' '
hd_str += ' '.join( [f"valid*"])
# Generate test vectors
tvectors = [ hd_str ]
for i in range(nvectors):
vector = []
# Add input data
vector.append(1) #en=1
for j in range(width*width):
vector.append( bits_type(random.randint(INTMAX-255, INTMAX)) ) #generate current frame
for j in range(width*width):
vector.append( bits_type(random.randint(INTMIN, INTMIN+255))) #generate next frame
# Add output data
for k in range(0,side): #check Ix results
for l in range(0,side):
vector.append (vector[width*(k+1)+l+3] - vector[width*(k+1)+l+1])
for k in range(0,side): #check Iy results
for l in range(0,side):
vector.append(vector[(k+2)*width+l+1+1] -vector[k*width+l+1+1] )
for k in range(0,side):
for l in range(0,side):
vector.append(vector[width*width+(k+1)*width+l+1+1]-vector[(k+1)*width+l+1+1])
vector.append(1) #valid=1
tvectors.append( vector )
run_test_vector_sim( GradientVRTL(3), tvectors, dump_vcd, test_verilog )
def test_alu_add(dump_vcd, test_verilog):
dut = AluRTL()
config_model(dut, dump_vcd, test_verilog)
run_test_vector_sim(
dut,
[
('in0 in1 fn out* ops_eq* ops_lt* ops_ltu*'
),
[0x00000000, 0x00000000, 0, 0x00000000, '?', '?', '?'],
[0x0ffaa660, 0x00012304, 0, 0x0ffbc964, '?', '?', '?'],
#pos-neg
[0x00132050, 0xd6620040, 0, 0xd6752090, '?', '?', '?'],
[0xfff0a440, 0x00004450, 0, 0xfff0e890, '?', '?', '?'],
# neg-neg
[0xfeeeeaa3, 0xf4650000, 0, 0xf353eaa3, '?', '?', '?'],
])
def test_single_one(dump_vcd, test_verilog):
dut = IntMulVarLatCalcShamtRTL()
config_model(dut, dump_vcd, test_verilog)
run_test_vector_sim(dut, [
('in_ out*'),
[0x00000000, 8],
[0x00000001, 1],
[0x00000002, 1],
[0x00000004, 2],
[0x00000008, 3],
[0x00000010, 4],
[0x00000020, 5],
[0x00000040, 6],
[0x00000080, 7],
])
def test_alu_sub(dump_vcd, test_verilog):
dut = AluRTL()
config_model(dut, dump_vcd, test_verilog)
run_test_vector_sim(
dut,
[
('in0 in1 fn out* ops_eq* ops_lt* ops_ltu*'
),
[0x00000000, 0x00000000, 1, 0x00000000, '?', '?', '?'],
[0x0ffaa660, 0x00012304, 1, 0x0ff9835c, '?', '?', '?'],
# pos-neg
[0x00132050, 0xd6620040, 1, 0x29b12010, '?', '?', '?'],
[0xfff0a440, 0x00004450, 1, 0xfff05ff0, '?', '?', '?'],
# neg-neg
[0xfeeeeaa3, 0xf4650000, 1, 0x0a89eaa3, '?', '?', '?'],
])
def test_alu_sra(dump_vcd, test_verilog):
dut = AluRTL()
config_model(dut, dump_vcd, test_verilog)
run_test_vector_sim(dut, [
('in0 in1 fn out* ops_eq* ops_lt* ops_ltu*'
),
[0x00000000, 0x00000000, 10, 0x00000000, '?', '?', '?'],
[0x05050505, 0x00000001, 10, 0x02828282, '?', '?', '?'],
[0x05050505, 0x00000002, 10, 0x01414141, '?', '?', '?'],
[0x05050505, 0xffffff01, 10, 0x02828282, '?', '?', '?'],
[0x05050505, 0xffffff02, 10, 0x01414141, '?', '?', '?'],
[0x05050505, 0x00000004, 10, 0x00505050, '?', '?', '?'],
[0x80808080, 0x00000008, 10, 0xff808080, '?', '?', '?'],
[0x80808080, 0x0000000f, 10, 0xffff0101, '?', '?', '?'],
[0x80808080, 0x00000010, 10, 0xffff8080, '?', '?', '?'],
[0x80808080, 0x0000001f, 10, 0xffffffff, '?', '?', '?'],
[0xffffffff, 0x0000001f, 10, 0xffffffff, '?', '?', '?'],
])
def test_random(nports, nbits, dump_vcd, test_verilog):
nvectors = 10
bits_type = mk_bits(nbits)
hd_str = 'in_ out*'
# Generate test vectors
tvectors = [hd_str]
for i in range(nvectors):
vector, tmp = [], []
# Add input data
for j in range(nports):
tmp.append(bits_type(random.randint(0, 1024)))
vector.append(concat(*tmp))
# Add output data
vector.append(vector[0])
tvectors.append(vector)
run_test_vector_sim(PassThroughV2RTL(nports, nbits), tvectors, dump_vcd,
test_verilog)
def test_basic( dump_vcd, test_verilog ):
nvectors = 1 #numer of the random vectors
side = 3
bits_type = mk_bits(32)
width =side+2
hd_str = ' '.join( [ f"en"])
hd_str += ' '
hd_str += ' '.join( [ f"current_frame[{i}]" for i in range(width*width) ] )
hd_str += ' '
hd_str += ' '.join( [ f"next_frame[{i}]" for i in range(width*width) ] )
hd_str += ' '
hd_str += ' '.join( [ f"Ix[{i}]*" for i in range(side*side) ] )
hd_str += ' '
hd_str += ' '.join( [ f"Iy[{i}]*" for i in range(side*side) ] )
hd_str += ' '
hd_str += ' '.join( [ f"It[{i}]*" for i in range(side*side) ] )
hd_str += ' '
hd_str += ' '.join( [f"valid*"])
# Generate test vectors
tvectors = [ hd_str ]
for i in range(nvectors):
vector = []
# Add input data
vector.append(1) #en=1
for j in range(width*width):
vector.append( bits_type(j) ) #generate current frame
for j in range(width*width):
vector.append( bits_type(j)) #generate next frame
# Add output data
for k in range(0,side*side): #check Ix results
vector.append(2)
for k in range(0,side*side): #check Iy results
vector.append(10)
for k in range(0,side*side):
vector.append(0)
vector.append(1) #valid=1
tvectors.append( vector )
run_test_vector_sim( GradientVRTL(3), tvectors, dump_vcd, test_verilog )
def test_directed(dump_vcd, test_verilog):
# 4 Bits16 ports
run_test_vector_sim(PassThroughV2RTL(4, 16), [
"in_ out*",
[
concat(b16(0), b16(0), b16(0), b16(0)),
concat(b16(0), b16(0), b16(0), b16(0))
],
[
concat(b16(1), b16(0), b16(3), b16(3)),
concat(b16(1), b16(0), b16(3), b16(3))
],
[
concat(b16(-1), b16(42), b16(30), b16(25)),
concat(b16(-1), b16(42), b16(30), b16(25))
],
[
concat(b16(42), b16(-1), b16(20), b16(16)),
concat(b16(42), b16(-1), b16(20), b16(16))
],
], dump_vcd, test_verilog)
def test_random( nports, nbits, dump_vcd, test_verilog ):
nvectors = 10
bits_type = mk_bits(nbits)
hd_str = ' '.join( [ f"in_[{i}]" for i in range(nports) ] )
hd_str += ' '
hd_str += ' '.join( [ f"out[{i}]*" for i in range(nports) ] )
# Generate test vectors
tvectors = [ hd_str ]
for i in range(nvectors):
vector = []
# Add input data
for j in range(nports):
vector.append( bits_type( random.randint(0, 1024) ) )
# Add output data
for j in range(nports):
vector.append( vector[j] )
tvectors.append( vector )
run_test_vector_sim( PassThroughV1RTL( nports, nbits ), tvectors, dump_vcd, test_verilog )
def test_direct_128x256_mask4(dump_vcd, test_verilog):
dut = SramRTL(128, 256, mask_size=4)
config_model(dut, dump_vcd, test_verilog)
header_str = \
( "port0_val", "port0_type", "port0_wben", "port0_idx", "port0_wdata", "port0_rdata*" )
run_test_vector_sim(
dut,
[
header_str,
# val type wben idx wdata rdata
[1, 1, 0b0001, 0x00, 0x00000000, '?'], # one at a time
[1, 0, 0b0001, 0x00, 0x00000000, '?'],
[0, 0, 0b0001, 0x00, 0x00000000, 0x00000000],
[1, 1, 0b0001, 0x00, 0xdeadbeef, '?'],
[1, 0, 0b0001, 0x00, 0x00000000, '?'],
[0, 0, 0b0001, 0x00, 0x00000000, 0xdeadbeef],
[1, 1, 0b0001, 0x01, 0xcafecafe, '?'],
[1, 0, 0b0001, 0x01, 0x00000000, '?'],
[0, 0, 0b0001, 0x00, 0x00000000, 0xcafecafe],
[1, 1, 0b0001, 0x2f, 0x0a0a0a0a, '?'],
[1, 0, 0b0001, 0x2f, 0x00000000, '?'],
[0, 0, 0b0001, 0x00, 0x00000000, 0x0a0a0a0a],
[1, 1, 0b0001, 0x2e, 0x0b0b0b0b, '?'], # streaming reads
[1, 0, 0b0001, 0x2e, 0x00000000, '?'],
[1, 0, 0b0001, 0x2f, 0x00000000, 0x0b0b0b0b],
[1, 0, 0b0001, 0x01, 0x00000000, 0x0a0a0a0a],
[1, 0, 0b0001, 0x00, 0x00000000, 0xcafecafe],
[0, 0, 0b0001, 0x00, 0x00000000, 0xdeadbeef],
[1, 1, 0b0001, 0x2d, 0x0c0c0c0c, '?'], # streaming writes/reads
[1, 0, 0b0001, 0x2d, 0x00000000, '?'],
[1, 1, 0b0001, 0x2c, 0x0d0d0d0d, 0x0c0c0c0c],
[1, 0, 0b0001, 0x2c, 0x00000000, '?'],
[1, 1, 0b0001, 0x2b, 0x0e0e0e0e, 0x0d0d0d0d],
[1, 0, 0b0001, 0x2b, 0x00000000, '?'],
[0, 0, 0b0001, 0x00, 0x00000000, 0x0e0e0e0e],
])
def test_direct_32x256(dump_vcd, test_verilog):
dut = SramRTL(32, 256)
config_model(dut, dump_vcd, test_verilog)
run_test_vector_sim(
dut,
[
header_str,
# val type idx wdata rdata
[1, 1, 0x00, 0x00000000, '?'], # one at a time
[1, 0, 0x00, 0x00000000, '?'],
[0, 0, 0x00, 0x00000000, 0x00000000],
[1, 1, 0x00, 0xdeadbeef, '?'],
[1, 0, 0x00, 0x00000000, '?'],
[0, 0, 0x00, 0x00000000, 0xdeadbeef],
[1, 1, 0x01, 0xcafecafe, '?'],
[1, 0, 0x01, 0x00000000, '?'],
[0, 0, 0x00, 0x00000000, 0xcafecafe],
[1, 1, 0x1f, 0x0a0a0a0a, '?'],
[1, 0, 0x1f, 0x00000000, '?'],
[0, 0, 0x00, 0x00000000, 0x0a0a0a0a],
[1, 1, 0x1e, 0x0b0b0b0b, '?'], # streaming reads
[1, 0, 0x1e, 0x00000000, '?'],
[1, 0, 0x1f, 0x00000000, 0x0b0b0b0b],
[1, 0, 0x01, 0x00000000, 0x0a0a0a0a],
[1, 0, 0x00, 0x00000000, 0xcafecafe],
[0, 0, 0x00, 0x00000000, 0xdeadbeef],
[1, 1, 0x1d, 0x0c0c0c0c, '?'], # streaming writes/reads
[1, 0, 0x1d, 0x00000000, '?'],
[1, 1, 0x1c, 0x0d0d0d0d, 0x0c0c0c0c],
[1, 0, 0x1c, 0x00000000, '?'],
[1, 1, 0x1b, 0x0e0e0e0e, 0x0d0d0d0d],
[1, 0, 0x1b, 0x00000000, '?'],
[0, 0, 0x00, 0x00000000, 0x0e0e0e0e],
])
def test_direct_16x32(dump_vcd, test_verilog):
dut = SramRTL(16, 32)
config_model(dut, dump_vcd, test_verilog)
run_test_vector_sim(
dut,
[
header_str,
# val type idx wdata rdata
[1, 1, 0x0, 0x0000, '?'], # one at a time
[1, 0, 0x0, 0x0000, '?'],
[0, 0, 0x0, 0x0000, 0x0000],
[1, 1, 0x0, 0xbeef, '?'],
[1, 0, 0x0, 0x0000, '?'],
[0, 0, 0x0, 0x0000, 0xbeef],
[1, 1, 0x1, 0xcafe, '?'],
[1, 0, 0x1, 0x0000, '?'],
[0, 0, 0x0, 0x0000, 0xcafe],
[1, 1, 0xf, 0x0a0a, '?'],
[1, 0, 0xf, 0x0000, '?'],
[0, 0, 0x0, 0x0000, 0x0a0a],
[1, 1, 0xe, 0x0b0b, '?'], # streaming reads
[1, 0, 0xe, 0x0000, '?'],
[1, 0, 0xf, 0x0000, 0x0b0b],
[1, 0, 0x1, 0x0000, 0x0a0a],
[1, 0, 0x0, 0x0000, 0xcafe],
[0, 0, 0x0, 0x0000, 0xbeef],
[1, 1, 0xd, 0x0c0c, '?'], # streaming writes/reads
[1, 0, 0xd, 0x0000, '?'],
[1, 1, 0xc, 0x0d0d, 0x0c0c],
[1, 0, 0xc, 0x0000, '?'],
[1, 1, 0xb, 0x0e0e, 0x0d0d],
[1, 0, 0xb, 0x0000, '?'],
[0, 0, 0x0, 0x0000, 0x0e0e],
])
def test_immgen(dump_vcd, test_verilog):
dut = ImmGenRTL()
config_model(dut, dump_vcd, test_verilog)
run_test_vector_sim(
dut,
[
('imm_type inst imm*'),
[
0, 0b11111111111100000000000000000000,
0b11111111111111111111111111111111
], # I-imm
[
0, 0b00000000000011111111111111111111,
0b00000000000000000000000000000000
], # I-imm
[
0, 0b01111111111100000000000000000000,
0b00000000000000000000011111111111
], # I-imm
[
0, 0b11111111111000000000000000000000,
0b11111111111111111111111111111110
], # I-imm
[
1, 0b11111110000000000000111110000000,
0b11111111111111111111111111111111
], # S-imm
[
1, 0b00000001111111111111000001111111,
0b00000000000000000000000000000000
], # S-imm
[
1, 0b01111110000000000000111110000000,
0b00000000000000000000011111111111
], # S-imm
[
1, 0b11111110000000000000111100000000,
0b11111111111111111111111111111110
], # S-imm
[
2, 0b11111110000000000000111110000000,
0b11111111111111111111111111111110
], # B-imm
[
2, 0b00000001111111111111000001111111,
0b00000000000000000000000000000000
], # B-imm
[
2, 0b11000000000000000000111100000000,
0b11111111111111111111010000011110
], # B-imm
[
3, 0b11111111111111111111000000000000,
0b11111111111111111111000000000000
], # U-imm
[
3, 0b00000000000000000000111111111111,
0b00000000000000000000000000000000
], # U-imm
[
4, 0b11111111111111111111000000000000,
0b11111111111111111111111111111110
], # J-imm
[
4, 0b00000000000000000001111111111111,
0b00000000000000000001000000000000
], # J-imm
[
4, 0b01000000000010011001000000000000,
0b00000000000010011001010000000000
], # J-imm
])
def test_random(nbits, dump_vcd, test_verilog):
tvec_random = [[randint(0, 2**nbits - 1) for _ in range(4)]
for _ in range(20)]
run_test_vector_sim(SortUnitStructRTL(nbits),
mk_test_vector_table(3, tvec_random), dump_vcd,
test_verilog)