def __init__(self, **kwargs):
super().__init__(description='Microblaze log buffer', **kwargs)
# Creation. memBase is either the register bus server (srp, rce mapped memory, etc) or the device which
# contains this object. In most cases the parent and memBase are the same but they can be
# different in more complex bus structures. They will also be different for the top most node.
# The setMemBase call can be used to update the memBase for this Device. All sub-devices and local
# blocks will be updated.
#############################################
# Create block / variable combinations
#############################################
#Setup registers & variables
self.add((pr.Variable(name='MemPointer',
description='MemInfo',
offset=0x00000000,
bitSize=16,
bitOffset=0,
base='hex',
mode='RO'),
pr.Variable(name='MemLength',
description='MemInfo',
offset=0x00000000,
bitSize=16,
bitOffset=16,
base='hex',
mode='RO')))
self.add(
pr.Variable(name='MemLow',
description='MemLow',
offset=0x01 * 4,
bitSize=2048 * 8,
bitOffset=0,
base='string',
mode='RO'))
self.add(
pr.Variable(name='MemHigh',
description='MemHigh',
offset=0x201 * 4,
bitSize=2044 * 8,
bitOffset=0,
base='string',
mode='RO'))
def addPair(name, description, offset):
"""Add a Raw ADC register variable and corresponding converted value Variable"""
self.add(
pr.Variable(name=name + "Raw",
offset=offset,
bitSize=12,
bitOffset=0,
units="3.3V/4095",
base='hex',
mode='RW',
description=description))
self.add(
pr.Variable(name=name,
mode='RO',
base='string',
units='V',
getFunction=dac.convtFloat,
dependencies=[self.variables[name + "Raw"]]))
def __init__(self, name="matrix"):
super(self.__class__, self).__init__(name, "CHESS2 Matrix Data",
memBase=None, hidden=True, expand=False)
# Init the variables to all ones (Note: all config bits are active LOW)
self._pixel = [[0x3F for row in range(128)] for col in range(32)]
# Create the PyRogue software variables
for col in range(32):
for row in range(128):
# Common string
pixel = 'col%02irow%03i'%(col,row)
# Add the software variables
self.add(pr.Variable(name=(pixel),
description='Pixel Configuration',
base='hex', mode='RW',bitSize=6,
setFunction='dev._pixel[%d][%d] = value'%(col,row),
getFunction='value = dev._pixel[%d][%d]'%(col,row)))
def __init__(self,
name="Chess2Test",
memBase=None,
offset=0,
hidden=False,
expand=True,
enabled=False):
super(self.__class__, self).__init__(name,
"CHESS2 Test structure Interface",
memBase=memBase,
offset=offset,
hidden=hidden,
expand=expand,
enabled=enabled)
#################################################################################################
# Using the atlas-chess2/firmware/submodules/surf/protocols/saci/rtl/AxiLiteSaciMaster.vhd module
# AXI_Lite_Address[31:24] = Ignored
# AXI_Lite_Address[23:22] = SACI Chip Select [1:0]
# AXI_Lite_Address[21] = Ignored
# AXI_Lite_Address[20:14] = SACI command [6:0]
# AXI_Lite_Address[13:2] = SACI address [11:0]
# AXI_Lite_Address[1:0] = Ignored
# AXI_Lite_Data[31:0] = SACI data [31:0]
#################################################################################################
# Define the command bit mask
cmd0x1 = (0x1 << 14)
# Define the row and col bit size
rowBitSize = 7
colBitSize = 5
# Define all the global registers
self.add(
pr.Variable(name='RowPointer',
description='Row Pointer',
offset=(cmd0x1 | (4 * 0x1)),
bitSize=rowBitSize,
bitOffset=0,
base='hex',
mode='RW'))
self.add(
pr.Variable(name='ColPointer',
description='Column Pointer',
offset=(cmd0x1 | (4 * 0x3)),
bitSize=colBitSize,
bitOffset=0,
base='hex',
mode='RW'))
self.add(
pr.Variable(name='Casc',
description='Casc',
offset=(cmd0x1 | (4 * 0x5)),
bitSize=10,
bitOffset=0,
base='hex',
mode='RW'))
self.add(
pr.Variable(name='ColMux',
description='ColMux',
offset=(cmd0x1 | (4 * 0x5)),
bitSize=5,
bitOffset=10,
base='hex',
mode='RW'))
self.add(
pr.Variable(name='BL',
description='BL',
offset=(cmd0x1 | (4 * 0x6)),
bitSize=10,
bitOffset=0,
base='hex',
mode='RW'))
self.add(
pr.Variable(name='CascPD',
description='CascPD',
offset=(cmd0x1 | (4 * 0x6)),
bitSize=1,
bitOffset=10,
base='bool',
mode='RW'))
self.add(
pr.Variable(name='BLPD',
description='BLPD',
offset=(cmd0x1 | (4 * 0x6)),
bitSize=1,
bitOffset=11,
base='bool',
mode='RW'))
self.add(
pr.Variable(name='PixPD',
description='PixPD',
offset=(cmd0x1 | (4 * 0x6)),
bitSize=1,
bitOffset=12,
base='bool',
mode='RW'))
self.add(
pr.Variable(name='BLRPD',
description='BLRPD',
offset=(cmd0x1 | (4 * 0x6)),
bitSize=1,
bitOffset=13,
base='bool',
mode='RW'))
self.add(
pr.Variable(name='Pix',
description='Pix',
offset=(cmd0x1 | (4 * 0x7)),
bitSize=10,
bitOffset=0,
base='hex',
mode='RW'))
self.add(
pr.Variable(name='BLR',
description='BLR',
offset=(cmd0x1 | (4 * 0x8)),
bitSize=10,
bitOffset=0,
base='hex',
mode='RW'))
def __init__(self, name="chargeInj", memBase=None, offset=0, hidden=False, expand=True):
super(self.__class__, self).__init__(name, "Charge Injection Module",
memBase=memBase, offset=offset, hidden=hidden, expand=expand)
self.add(pr.Variable(name='pulseWidthRaw', units="1/320MHz",description='pulse width minus one', offset=0x14, bitSize=15, bitOffset=0, base='hex', mode='RW'))
self.add(pr.Variable(name='pulseWidth', mode = 'RO', units="ns", base='string', getFunction=self.nsPulse, dependencies=[self.variables['pulseWidthRaw']]))
self.add(pr.Variable(name='pulseDelayRaw', units="1/320MHz",description='pulse delay minus one', offset=0x14, bitSize=15, bitOffset=16, base='hex', mode='RW'))
self.add(pr.Variable(name='pulseDelay', mode = 'RO', units="ns", base='string', getFunction=self.nsPulse, dependencies=[self.variables['pulseDelayRaw']]))
self.add(pr.Variable(name='invPulse', description='Invert the pulse', offset=0x18, bitSize=1, bitOffset=0, base='bool', mode='RW'))
self.add(pr.Variable(name='calPulseInh', description='Inhibites Qinj pulse to be sent out', offset=0x1C, bitSize=1, bitOffset=0, base='bool', mode='RW'))
for i in range(3):
self.add(pr.Variable(name='hitDetValid%01i_%01i'%(i,0), offset=(4*i), bitSize=1, bitOffset=13, base='bool', mode='RO'))
self.add(pr.Variable(name='hitDetFlag%01i_%01i'%(i,0), offset=(4*i), bitSize=1, bitOffset=12, base='bool', mode='RO'))
self.add(pr.Variable(name='hitDetCol%01i_%01i'%(i,0), offset=(4*i), bitSize=5, bitOffset=7, base='hex', mode='RO'))
self.add(pr.Variable(name='hitDetRow%01i_%01i'%(i,0), offset=(4*i), bitSize=7, bitOffset=0, base='hex', mode='RO'))
self.add(pr.Variable(name='hitDetTimeRaw%01i_%01i'%(i,0), units="1/320MHz", description=' ', offset=(4*i), bitSize=16, bitOffset=16, base='hex', mode='RO'))
self.add(pr.Variable(name='hitDetTime%01i_%01i'%(i,0), mode = 'RO', units="ns", base='string', getFunction=self.nsTdc, dependencies=[self.variables['hitDetTimeRaw%01i_%01i'%(i,0)]]))
for j in range(1,8):
for i in range(3):
self.add(pr.Variable(name='hitDetValid%01i_%01i'%(i,j), offset=(4*i+((j+1)*16)), bitSize=1, bitOffset=13, base='bool', mode='RO'))
self.add(pr.Variable(name='hitDetFlag%01i_%01i'%(i,j), offset=(4*i+((j+1)*16)), bitSize=1, bitOffset=12, base='bool', mode='RO'))
self.add(pr.Variable(name='hitDetCol%01i_%01i'%(i,j), offset=(4*i+((j+1)*16)), bitSize=5, bitOffset=7, base='hex', mode='RO'))
self.add(pr.Variable(name='hitDetRow%01i_%01i'%(i,j), offset=(4*i+((j+1)*16)), bitSize=7, bitOffset=0, base='hex', mode='RO'))
self.add(pr.Variable(name='hitDetTimeRaw%01i_%01i'%(i,j), units="1/320MHz", description=' ', offset=(4*i+((j+1)*16)), bitSize=16, bitOffset=16, base='hex', mode='RO'))
self.add(pr.Variable(name='hitDetTime%01i_%01i'%(i,j), mode = 'RO', units="ns", base='string', getFunction=self.nsTdc, dependencies=[self.variables['hitDetTimeRaw%01i_%01i'%(i,j)]]))
self.add(pr.Variable(name = "calPulseVar", description = "Calibration Pulse",
offset=0x10, bitSize=1, bitOffset=0, base='bool', mode='SL', hidden=True))
self.add(pr.Command(name='calPulse',description='Calibration Pulse',base='None',
function="""\
dev.calPulseVar.set(1)
"""))
def __init__(self,
name="sysReg",
memBase=None,
offset=0,
hidden=False,
expand=True):
super(self.__class__, self).__init__(name,
"System Register Module",
memBase=memBase,
offset=offset,
hidden=hidden,
expand=expand)
self.add(
pr.Variable(name='refLockedCnt',
description='Reference clock Locked Status Counter',
offset=0x000,
bitSize=32,
bitOffset=0,
base='hex',
mode='RO'))
self.add(
pr.Variable(name='refLocked',
description='Reference clock Locked Status',
offset=0x100,
bitSize=1,
bitOffset=0,
base='bool',
mode='RO'))
self.add(
pr.Variable(name='refClkFreq',
description='Reference clock frequency (units of Hz)',
units='Hz',
offset=0x1FC,
bitSize=32,
bitOffset=0,
base='uint',
mode='RO'))
self.add(
pr.Variable(
name='refSelect',
description=
'0x0 = local 40 MHz OSC, 0x1 = external 40 MHz reference',
enum={
0: 'LOCAL_40MHZ_OSC',
1: 'EXTERNAL_40MHZ_OSC'
},
offset=0x800,
bitSize=1,
bitOffset=0,
base='enum',
mode='RW'))
self.add(
pr.Variable(
name='timingMode',
description=
'0x0 = LEMO Triggering, 0x1 = PGP Triggering, 0x2 = EVR Triggering',
enum={
0: 'TIMING_LEMO_TRIG_C',
1: 'TIMING_PGP_TRIG_C',
2: 'TIMING_SLAC_EVR_C',
3: 'TIMING_RESERVED'
},
offset=0x804,
bitSize=2,
bitOffset=0,
base='enum',
mode='RW'))
self.add(
pr.Variable(name='pllRst',
description='PLL reset',
offset=0x808,
bitSize=1,
bitOffset=0,
base='bool',
mode='WO'))
self.add(
pr.Variable(name='dlyRst',
description='Delay FIFOs reset',
offset=0x80C,
bitSize=1,
bitOffset=0,
base='bool',
mode='WO'))
self.add(
pr.Variable(
name='dlyTiming',
description=
'ASIC timingpath delay FIFO configuration (units of 1/320MHz)',
offset=0x810,
bitSize=12,
bitOffset=0,
base='hex',
mode='RW'))
self.add(
pr.Variable(
name='dlyChess',
description=
'ASIC datapath delay FIFO configuration (units of 1/320MHz)',
offset=0x814,
bitSize=12,
bitOffset=0,
base='hex',
mode='RW'))
self.add(
pr.Variable(name='destId',
description='ASIC packet header DEST ID',
offset=0x818,
bitSize=6,
bitOffset=0,
base='hex',
mode='RW'))
self.add(
pr.Variable(name='frameType',
description='ASIC packet header frame type',
offset=0x81C,
bitSize=32,
bitOffset=0,
base='hex',
mode='RW'))
self.add(
pr.Variable(
name='pktWordSize',
description='ASIC Packet Size (in units of 16-bits words)',
offset=0x820,
bitSize=8,
bitOffset=0,
base='hex',
mode='RW'))
self.add(
pr.Variable(
name='chessClkOe',
description='CHESS clock output enable',
# enum = {0:'CLOCKS_DISABLED',1:'CLOCKS_ENABLED'},
offset=0x824,
bitSize=1,
bitOffset=0,
base='bool',
mode='RW'))
self.add(
pr.Variable(name='forceHardReset',
description='ForceHardReset',
offset=0x828,
bitSize=1,
bitOffset=0,
base='bool',
mode='RW'))
self.add(
pr.Variable(name='debugSendCnt',
description='DebugSendCnt',
offset=0x82C,
bitSize=1,
bitOffset=0,
base='bool',
mode='RW'))
self.add(
pr.Variable(name='rollOverEn',
description='RollOverEn',
offset=0xf00,
bitSize=1,
bitOffset=0,
base='hex',
mode='RW'))
self.add(
pr.Command(name='counterReset',
description='CounterReset',
offset=0xf10,
bitSize=1,
bitOffset=0,
function=pr.Command.touch))
self.add(
pr.Variable(name="softTrigVar",
description="Software Trigger",
offset=0xf14,
bitSize=1,
bitOffset=0,
base='bool',
mode='SL',
hidden=True))
self.add(
pr.Command(name='softTrig',
description='Software Trigger',
base='None',
function="""\
dev.softTrigVar.set(1)
"""))
self.add(
pr.Variable(name='softReset',
description='SoftReset',
offset=0xff8,
bitSize=1,
bitOffset=0,
base='bool',
mode='SL',
hidden=True))
self.add(
pr.Variable(name='hardReset',
description='HardReset',
offset=0xffc,
bitSize=1,
bitOffset=0,
base='hex',
mode='WO',
hidden=False))
def create(name='axiVersionEpix100a', offset=0, memBase=None, hidden=False, enabled=True):
"""Create the axiVersion device"""
#In order to easely compare GedDAQ address map with the eprix rogue address map
#it is defined the addrSize variable
addrSize = 4
# Creation. memBase is either the register bus server (srp, rce mapped memory, etc) or the device which
# contains this object. In most cases the parent and memBase are the same but they can be
# different in more complex bus structures. They will also be different for the top most node.
# The setMemBase call can be used to update the memBase for this Device. All sub-devices and local
# blocks will be updated.
dev = pyrogue.Device(name=name, memBase=memBase, offset=offset, hidden=hidden, size=0x1000,
description='AXI-Lite based common version block', enabled=enabled)
#############################################
# Create block / variable combinations
#############################################
# Next create a list of variables associated with this block.
# base has two functions. If base = 'string' then the block is treated as a string (see BuildStamp)
# otherwise the value is retrieved or set using:
# setUInt(self.bitOffset,self.bitSize,value) or getUInt(self.bitOffset,self.bitSize)
# otherwise base is used by a higher level interface (GUI, etc) to determine display mode
# Allowed modes are RO, WO, RW or SL. SL indicates registers can be written but only
# when executing commands (not accessed during writeAll and writeStale calls
#Setup registers & variables
dev.add(pyrogue.Variable(name='fpgaVersion', description='FPGA firmware version number',
offset=0x00*addrSize, bitSize=32, bitOffset=0, base='hex', mode='RO'))
# Example of using setFunction and getFunction. setFunction and getFunctions are defined in the class
# at the bottom. getFunction is defined as a series of python calls. When using the defined
# function the scope is relative to the location of the function defintion. A pointer to the variable
# and passed value are provided as args. See UserConstants below for an alernative method.
dev.add(pyrogue.Variable(name='runTriggerEnable', description='Enable external run trigger',
offset=0x01*addrSize, bitSize=1, bitOffset=0, base='bool', mode='RW'))
dev.add(pyrogue.Variable(name='runTriggerDelay', description='Run trigger delay',
offset=0x02*addrSize, bitSize=32, bitOffset=0, base='hex', mode='RW'))
dev.add(pyrogue.Variable(name='daqTriggerEnable', description='Enable external run trigger',
offset=0x03*addrSize, bitSize=1, bitOffset=0, base='bool', mode='RW'))
dev.add(pyrogue.Variable(name='daqTriggerDelay', description='Run trigger delay',
offset=0x04*addrSize, bitSize=32, bitOffset=0, base='hex', mode='RW'))
dev.add(pyrogue.Variable(name='acqCount', description='Acquisition counter',
offset=0x05*addrSize, bitSize=32, bitOffset=0, base='hex', mode='RO'))
dev.add(pyrogue.Variable(name='acqReset', description='Reset acquisition counter',
offset=0x06*addrSize, bitSize=32, bitOffset=0, base='hex', mode='WO'))
dev.add(pyrogue.Variable(name='dacData', description='Sets analog DAC (MAX5443)',
offset=0x07*addrSize, bitSize=16, bitOffset=0, base='hex', mode='RW'))
dev.add(pyrogue.Variable(name='powerEnable', description='Analog power enable',
offset=0x08*addrSize, bitSize=3, bitOffset=0, base='hex', mode='RW'))
dev.add(pyrogue.Variable(name='frameCount', description='Frame counter',
offset=0x0B*addrSize, bitSize=32, bitOffset=0, base='hex', mode='RO'))
dev.add(pyrogue.Variable(name='frameReset', description='Reset frame counter',
offset=0x0C*addrSize, bitSize=32, bitOffset=0, base='hex', mode='WO'))
dev.add(pyrogue.Variable(name='asicMask', description='ASIC mask bits for the SACI access',
offset=0x0D*addrSize, bitSize=3, bitOffset=0, base='hex', mode='RW'))
#Setup registers & variables
dev.add(pyrogue.Variable(name='baseClock', description='FPGA base clock frequency',
offset=0x10*addrSize, bitSize=32, bitOffset=0, base='hex', mode='RO'))
#Autotriggers
dev.add(pyrogue.Variable(name='autoRunEnable', description='Enable auto run trigger',
offset=0x11*addrSize, bitSize=1, bitOffset=0, base='bool', mode='RW'))
dev.add(pyrogue.Variable(name='autoRunPeriod', description='Auto run trigger period',
offset=0x12*addrSize, bitSize=32, bitOffset=0, base='hex', mode='RW'))
dev.add(pyrogue.Variable(name='autoDaqEnable', description='Enable auto DAQ trigger',
offset=0x13*addrSize, bitSize=1, bitOffset=0, base='bool', mode='RW'))
dev.add(pyrogue.Variable(name='outPipelineDelay', description='Number of clock cycles to delay ASIC digital output bit',
offset=0x1F*addrSize, bitSize=8, bitOffset=0, base='hex', mode='RW'))
dev.add(pyrogue.Variable(name='acqToAsicR0Delay', description='Delay (in 10ns) between system acq and ASIC reset pulse',
offset=0x20*addrSize, bitSize=32, bitOffset=0, base='hex', mode='RW'))
dev.add(pyrogue.Variable(name='asicR0ToAsicAcq', description='Delay (in 10ns) between ASIC reset pulse and ASIC integration window',
offset=0x21*addrSize, bitSize=32, bitOffset=0, base='hex', mode='RW'))
dev.add(pyrogue.Variable(name='asicAcqWidth', description='Width (in 10ns) of ASIC acq signal',
offset=0x22*addrSize, bitSize=32, bitOffset=0, base='hex', mode='RW'))
dev.add(pyrogue.Variable(name='asicAcqLToPPmatL', description='Delay (in 10ns) between ASIC acq dropping and power pulse signal falling',
offset=0x23*addrSize, bitSize=32, bitOffset=0, base='hex', mode='RW'))
dev.add(pyrogue.Variable(name='asicRoClkHalfT', description='Width (in 10ns) of half of readout clock (10 = 5MHz)',
offset=0x24*addrSize, bitSize=32, bitOffset=0, base='hex', mode='RW'))
dev.add(pyrogue.Variable(name='adcReadsPerPixel', description='Number of ADC samples to record for each ASIC',
offset=0x25*addrSize, bitSize=32, bitOffset=0, base='hex', mode='RW'))
dev.add(pyrogue.Variable(name='adcClkHalfT', description='Width (in 8ns) of half clock period of ADC',
offset=0x26*addrSize, bitSize=32, bitOffset=0, base='hex', mode='RW'))
dev.add(pyrogue.Variable(name='totalPixelsToRead', description='Total numbers of pixels to be readout',
offset=0x27*addrSize, bitSize=32, bitOffset=0, base='hex', mode='RW'))
#change this definition to expose individual bit
#dev.add(pyrogue.Variable(name='asicPins', description='Manual ASIC pin controls',
# offset=0x29*addrSize, bitSize=6, bitOffset=0, base='hex', mode='RW'))
dev.add(pyrogue.Variable(name='asicGR', description='Manual ASIC pin controls',
offset=0x29*addrSize, bitSize=1, bitOffset=0, base='bool', mode='RW'))
dev.add(pyrogue.Variable(name='asicAcq', description='Manual ASIC pin controls',
offset=0x29*addrSize, bitSize=1, bitOffset=1, base='bool', mode='RW'))
dev.add(pyrogue.Variable(name='asicRO', description='Manual ASIC pin controls',
offset=0x29*addrSize, bitSize=1, bitOffset=2, base='bool', mode='RW'))
dev.add(pyrogue.Variable(name='asicPpmat', description='Manual ASIC pin controls',
offset=0x29*addrSize, bitSize=1, bitOffset=3, base='bool', mode='RW'))
dev.add(pyrogue.Variable(name='asicPpbe', description='Manual ASIC pin controls',
offset=0x29*addrSize, bitSize=1, bitOffset=4, base='bool', mode='RW'))
dev.add(pyrogue.Variable(name='asicRoClk', description='Manual ASIC pin controls',
offset=0x29*addrSize, bitSize=1, bitOffset=5, base='bool', mode='RW'))
#change this definition to expose individual bit
#dev.add(pyrogue.Variable(name='asicPinControl', description='Manual ASIC pin controls',
# offset=0x2A*addrSize, bitSize=11, bitOffset=0, base='hex', mode='RW'))
dev.add(pyrogue.Variable(name='asicPinGRControl', description='Manual ASIC pin controls',
offset=0x2A*addrSize, bitSize=1, bitOffset=0, base='bool', mode='RW'))
dev.add(pyrogue.Variable(name='asicPinAcqControl', description='Manual ASIC pin controls',
offset=0x2A*addrSize, bitSize=1, bitOffset=1, base='bool', mode='RW'))
dev.add(pyrogue.Variable(name='asicPinROControl', description='Manual ASIC pin controls',
offset=0x2A*addrSize, bitSize=1, bitOffset=2, base='bool', mode='RW'))
dev.add(pyrogue.Variable(name='asicPinPpmatControl', description='Manual ASIC pin controls',
offset=0x2A*addrSize, bitSize=1, bitOffset=3, base='bool', mode='RW'))
dev.add(pyrogue.Variable(name='asicPinPpbeControl', description='Manual ASIC pin controls',
offset=0x2A*addrSize, bitSize=1, bitOffset=4, base='bool', mode='RW'))
dev.add(pyrogue.Variable(name='asicPinROClkControl', description='Manual ASIC pin controls',
offset=0x2A*addrSize, bitSize=1, bitOffset=5, base='bool', mode='RW'))
dev.add(pyrogue.Variable(name='adcStreamMode', description='Manual ASIC pin controls',
offset=0x2A*addrSize, bitSize=1, bitOffset=6, base='bool', mode='RW'))
dev.add(pyrogue.Variable(name='adcPatternEnable', description='Manual ASIC pin controls',
offset=0x2A*addrSize, bitSize=1, bitOffset=7, base='bool', mode='RW'))
dev.add(pyrogue.Variable(name='ROMode', description='Manual ASIC pin controls',
offset=0x2A*addrSize, bitSize=1, bitOffset=8, base='bool', mode='RW'))
dev.add(pyrogue.Variable(name='asicR0Width', description='Width of R0 low pulse',
offset=0x2B*addrSize, bitSize=32, bitOffset=0, base='hex', mode='RW'))
dev.add(pyrogue.Variable(name='digitalCardId0', description='Digital Card Serial Number (low 32 bits)',
offset=0x30*addrSize, bitSize=32, bitOffset=0, base='hex', mode='RW'))
dev.add(pyrogue.Variable(name='digitalCardId1', description='Digital Card Serial Number (high 32 bits)',
offset=0x31*addrSize, bitSize=32, bitOffset=0, base='hex', mode='RW'))
dev.add(pyrogue.Variable(name='analogCardId0', description='Analog Card Serial Number (low 32 bits)',
offset=0x32*addrSize, bitSize=32, bitOffset=0, base='hex', mode='RW'))
dev.add(pyrogue.Variable(name='analogCardId1', description='Analog Card Serial Number (high 32 bits)',
offset=0x33*addrSize, bitSize=32, bitOffset=0, base='hex', mode='RW'))
dev.add(pyrogue.Variable(name='asicPreAcqTime', description='Sum of time delays leading to the ASIC ACQ pulse',
offset=0x39*addrSize, bitSize=32, bitOffset=0, base='hex', mode='RO'))
dev.add(pyrogue.Variable(name='asicPPmatToReadout', description='Delay (in 10ns) between Ppmat pulse and readout',
offset=0x3A*addrSize, bitSize=32, bitOffset=0, base='hex', mode='RW'))
dev.add(pyrogue.Variable(name='carrierCardId0', description='Carrier Card Serial Number (low 32 bits)',
offset=0x3B*addrSize, bitSize=32, bitOffset=0, base='hex', mode='RW'))
dev.add(pyrogue.Variable(name='carrierCardId1', description='Carrier Card Serial Number (high 32 bits)',
offset=0x3C*addrSize, bitSize=32, bitOffset=0, base='hex', mode='RW'))
dev.add(pyrogue.Variable(name='pgpTrigEn', description='Set to enable triggering over PGP. Disables the TTL trigger input',
offset=0x3D*addrSize, bitSize=1, bitOffset=0, base='bool', mode='RW'))
dev.add(pyrogue.Variable(name='monStreamEn', description='Set to enable monitor data stream over PGP',
offset=0x3E*addrSize, bitSize=1, bitOffset=0, base='bool', mode='RW'))
dev.add(pyrogue.Variable(name='tpsTiming', description='Delay TPS signal',
offset=0x40*addrSize, bitSize=16, bitOffset=0, base='hex', mode='RW'))
dev.add(pyrogue.Variable(name='tpsEdge', description='Sync TPS to rising or falling edge of Acq',
offset=0x40*addrSize, bitSize=1, bitOffset=16, base='bool', mode='RW'))
dev.add(pyrogue.Variable(name='swArmBit', description='Software arm bit',
offset=0x50*addrSize, bitSize=1, bitOffset=0, base='bool', mode='RW'))
dev.add(pyrogue.Variable(name='swTrgBit', description='Software trigger bit',
offset=0x51*addrSize, bitSize=1, bitOffset=0, base='bool', mode='WO'))
dev.add(pyrogue.Variable(name='triggerADCEn', description='Trigger ADC enable',
offset=0x52*addrSize, bitSize=1, bitOffset=0, base='bool', mode='RW'))
dev.add(pyrogue.Variable(name='triggerADCTh', description='Trigger ADC threshold',
offset=0x52*addrSize, bitSize=16, bitOffset=16, base='hex', mode='RW'))
dev.add(pyrogue.Variable(name='triggerADCMode', description='Trigger ADC mode',
offset=0x52*addrSize, bitSize=2, bitOffset=5, base='hex', mode='RW'))
dev.add(pyrogue.Variable(name='triggerADCChannel', description='Trigger ADC channel',
offset=0x52*addrSize, bitSize=4, bitOffset=2, base='hex', mode='RW'))
dev.add(pyrogue.Variable(name='triggerADCEdge', description='Trigger ADC edge',
offset=0x52*addrSize, bitSize=1, bitOffset=1, base='bool', mode='RW'))
dev.add(pyrogue.Variable(name='triggerHoldOff', description='Number of samples to wait after the trigger is armed',
offset=0x53*addrSize, bitSize=13, bitOffset=0, base='hex', mode='RW'))
dev.add(pyrogue.Variable(name='triggerTraceSkip', description='Number of samples to skip before recording starts',
offset=0x54*addrSize, bitSize=13, bitOffset=13, base='hex', mode='RW'))
dev.add(pyrogue.Variable(name='triggerTraceLength', description='Number of samples to record',
offset=0x54*addrSize, bitSize=13, bitOffset=0, base='hex', mode='RW'))
dev.add(pyrogue.Variable(name='inputChannelB', description='Select input channel B',
offset=0x55*addrSize, bitSize=5, bitOffset=5, base='hex', mode='RW'))
dev.add(pyrogue.Variable(name='inputChannelA', description='Select input channel A',
offset=0x55*addrSize, bitSize=5, bitOffset=0, base='hex', mode='RW'))
dev.add(pyrogue.Variable(name='RequestStartup', description='Request startup sequence',
offset=0x80*addrSize, bitSize=1, bitOffset=0, base='bool', mode='WO'))
dev.add(pyrogue.Variable(name='StartupDone', description='Startup sequence done',
offset=0x80*addrSize, bitSize=1, bitOffset=1, base='bool', mode='RO'))
dev.add(pyrogue.Variable(name='StartupFail', description='Startup sequence failed',
offset=0x80*addrSize, bitSize=1, bitOffset=2, base='bool', mode='RO'))
dev.add(pyrogue.Variable(name='requestConfDump', description='Request Conf. Dump',
offset=0x81*addrSize, bitSize=1, bitOffset=0, base='bool', mode='WO'))
dev.add(pyrogue.Variable(name='adcPipelineDelayA0', description='Number of samples to delay ADC reads of the ASIC0 channels',
offset=0x90*addrSize, bitSize=32, bitOffset=0, base='hex', mode='RW'))
dev.add(pyrogue.Variable(name='adcPipelineDelayA1', description='Number of samples to delay ADC reads of the ASIC1 channels',
offset=0x91*addrSize, bitSize=32, bitOffset=0, base='hex', mode='RW'))
dev.add(pyrogue.Variable(name='adcPipelineDelayA2', description='Number of samples to delay ADC reads of the ASIC2 channels',
offset=0x92*addrSize, bitSize=32, bitOffset=0, base='hex', mode='RW'))
dev.add(pyrogue.Variable(name='adcPipelineDelayA3', description='Number of samples to delay ADC reads of the ASIC3 channels',
offset=0x93*addrSize, bitSize=32, bitOffset=0, base='hex', mode='RW'))
dev.add(pyrogue.Variable(name='EnvData00', description='Thermistor0 temperature',
offset=0x140*addrSize, bitSize=32, bitOffset=0, base='hex', mode='RW'))
dev.add(pyrogue.Variable(name='EnvData01', description='Thermistor1 temperature',
offset=0x141*addrSize, bitSize=32, bitOffset=0, base='hex', mode='RW'))
dev.add(pyrogue.Variable(name='EnvData02', description='Humidity',
offset=0x142*addrSize, bitSize=32, bitOffset=0, base='hex', mode='RW'))
dev.add(pyrogue.Variable(name='EnvData03', description='ASIC analog current',
offset=0x143*addrSize, bitSize=32, bitOffset=0, base='hex', mode='RW'))
dev.add(pyrogue.Variable(name='EnvData04', description='ASIC digital current',
offset=0x144*addrSize, bitSize=32, bitOffset=0, base='hex', mode='RW'))
dev.add(pyrogue.Variable(name='EnvData05', description='Guard ring current',
offset=0x145*addrSize, bitSize=32, bitOffset=0, base='hex', mode='RW'))
dev.add(pyrogue.Variable(name='EnvData06', description='Detector bias current',
offset=0x146*addrSize, bitSize=32, bitOffset=0, base='hex', mode='RW'))
dev.add(pyrogue.Variable(name='EnvData07', description='Analog raw input voltage',
offset=0x147*addrSize, bitSize=32, bitOffset=0, base='hex', mode='RW'))
dev.add(pyrogue.Variable(name='EnvData08', description='Digital raw input voltage',
offset=0x148*addrSize, bitSize=32, bitOffset=0, base='hex', mode='RW'))
# Here we define MasterReset as mode 'SL' this will ensure it does not get written during
# writeAll and writeStale commands
# dev.add(pyrogue.Variable(name='masterResetVar', description='Optional User Reset',
# offset=0x06*addrSize, bitSize=1, bitOffset=0, base='bool', mode='SL', hidden=True))
# dev.add(pyrogue.Variable(name='fpgaReloadVar', description='Optional reload the FPGA from the attached PROM',
# offset=0x07*addrSize, bitSize=1, bitOffset=0, base='bool', mode='SL', hidden=True))
# dev.add(pyrogue.Variable(name='fpgaReloadAddress', description='Reload start address',
# offset=0x08*addrSize, bitSize=32, bitOffset=0, base='hex', mode='RW'))
# dev.add(pyrogue.Variable(name='counter', description='Free running counter', pollInterval=1,
# offset=0x09*addrSize, bitSize=32, bitOffset=0, base='hex', mode='RO'))
# Bool is not used locally. Access will occur just as a uint or hex. The GUI will know how to display it.
# dev.add(pyrogue.Variable(name='fpgaReloadHalt', description='Used to halt automatic reloads via AxiVersion',
# offset=0x0A*addrSize, bitSize=1, bitOffset=0, base='bool', mode='RW'))
# dev.add(pyrogue.Variable(name='upTimeCnt', description='Number of seconds since reset', pollInterval=1,
# offset=0x2C, bitSize=32, bitOffset=0, base='uint', units="seconds", mode='RO'))
# dev.add(pyrogue.Variable(name='deviceId', description='Device identification',
# offset=0x30, bitSize=32, bitOffset=0, base='hex', mode='RO'))
# for i in range(0,64):
#
# # Example of using setFunction and getFunction passed as strings. The scope is local to
# # the variable object with the passed value available as 'value' in the scope.
# # The get function must set the 'value' variable as a result of the function.
# dev.add(pyrogue.Variable(name='userConstant_%02i'%(i), description='Optional user input values',
# offset=0x400+(i*4), bitSize=32, bitOffset=0, base='hex', mode='RW',
# getFunction="""\
# value = self._block.getUInt(self.bitOffset,self.bitSize)
# """,
# setFunction="""\
# self._block.setUInt(self.bitOffset,self.bitSize,value)
# """))
# dev.add(pyrogue.Variable(name='UserConstants', description='User constants string',
# offset=0x100*addrSize, bitSize=256*8, bitOffset=0, base='string', mode='RO'))
# dev.add(pyrogue.Variable(name='buildStamp', description='Firmware build string',
# offset=0x200*addrSize, bitSize=256*8, bitOffset=0, base='string', mode='RO'))
#####################################
# Create commands
#####################################
# A command has an associated function. The function can be a series of
# python commands in a string. Function calls are executed in the command scope
# the passed arg is available as 'arg'. Use 'dev' to get to device scope.
dev.add(pyrogue.Command(name='masterReset',description='Master Reset',
function='dev.masterResetVar.post(1)'))
# A command can also be a call to a local function with local scope.
# The command object and the arg are passed
dev.add(pyrogue.Command(name='fpgaReload',description='Reload FPGA',
function=cmdFpgaReload))
dev.add(pyrogue.Command(name='counterReset',description='Counter Reset',
function='dev.counter.post(0)'))
# Example printing the arg and showing a larger block. The indentation will be adjusted.
# dev.add(pyrogue.Command(name='testCommand',description='Test Command',
# function="""\
# print("Someone executed the %s command" % (self.name))
# print("The passed arg was %s" % (arg))
# print("My device is %s" % (dev.name))
# """))
# Alternative function for CPSW compatability
# Pass a dictionary of numbered variable, value pairs to generate a CPSW sequence
dev.add(pyrogue.Command(name='testCpsw',description='Test CPSW',
function=collections.OrderedDict({ 'masterResetVar': 1,
'usleep': 100,
'counter': 1 })))
# Overwrite reset calls with local functions
dev.setResetFunc(resetFunc)
# Return the created device
return dev
def __init__(self, **kwargs):
super(self.__class__,
self).__init__(description="RCE Version and BSI register.",
**kwargs)
self.add(
pyrogue.Variable(name='fpgaVersion',
description='Fpga firmware version number',
offset=0x80000000,
bitsize=32,
bitoffset=0,
base='hex',
mode='RO'))
self.add(
pyrogue.Variable(name='scratchPad',
description='Scratchpad Register',
offset=0x80000004,
bitsize=32,
bitoffset=0,
base='hex',
mode='RW'))
self.add(
pyrogue.Variable(name='rceVersion',
description='RCE registers version number',
offset=0x80000008,
bitsize=32,
bitoffset=0,
base='hex',
mode='RO'))
self.add(
pyrogue.Variable(name='deviceDna',
description='Xilinx Device DNA Value',
offset=0x80000020,
bitsize=64,
bitoffset=0,
base='hex',
mode='RO'))
self.add(
pyrogue.Variable(name='eFuseValue',
description='Xilinx E-Fuse Value',
offset=0x80000030,
bitsize=32,
bitoffset=0,
base='hex',
mode='RO'))
self.add(
pyrogue.Variable(name='ethMode',
description='Ethernet Mode',
offset=0x80000034,
bitsize=32,
bitoffset=0,
base='hex',
mode='RO'))
self.add(
pyrogue.Variable(name='heartBeat',
description='A constantly incrementing value',
offset=0x80000038,
bitsize=32,
bitoffset=0,
pollInterval=1,
base='hex',
mode='RO'))
self.add(
pyrogue.Variable(name='gitHash',
description='GIT SHA-1 Hash',
offset=0x80000040,
bitSize=160,
bitOffset=0,
base='hex',
mode='RO'))
self.add(
pyrogue.Variable(name='buildStamp',
description='Firmware build string',
offset=0x80001000,
bitSize=256 * 8,
bitOffset=0,
base='string',
mode='RO'))
self.add(
pyrogue.Variable(name='serialNumber',
description='Serial Number',
offset=0x84000140,
bitSize=64,
bitOffset=0,
base='hex',
mode='RO'))
self.add(
pyrogue.Variable(name='atcaSlot',
description='ATCA Slot',
offset=0x84000148,
bitSize=8,
bitOffset=16,
base='hex',
mode='RO'))
self.add(
pyrogue.Variable(name='cobBay',
description='COB Bay',
offset=0x84000148,
bitSize=8,
bitOffset=8,
base='hex',
mode='RO'))
self.add(
pyrogue.Variable(name='cobElement',
description='COB Element',
offset=0x84000148,
bitSize=8,
bitOffset=0,
base='hex',
mode='RO'))
def __init__(self,
name="memReg",
memBase=None,
offset=0,
hidden=False,
expand=True):
super(self.__class__, self).__init__(name,
"Memory Register Module",
memBase=memBase,
offset=offset,
hidden=hidden,
expand=expand)
# dev.add(pyrogue.Variable(name='ssiPrintf', description='Retrieve data printed on the microblaze',
# offset=0x00040004, bitSize=1024*4, bitOffset=0, base='string', mode='RO'))
self.add(
pr.Variable(
name='chargInjStartEventReg',
description=
'Write to this register to invoque a irq to start the test',
offset=0x000,
bitSize=32,
bitOffset=0,
base='hex',
mode='RW'))
self.add(
pr.Variable(
name='chargInjHeartBeatReg',
description=
'Write to this register to invoque a irq to start the test',
offset=0x004,
bitSize=32,
bitOffset=0,
base='hex',
mode='RO',
pollInterval=1))
self.add(
pr.Variable(
name='chargInjNumEventsReg',
description=
'Write to this register to invoque a irq to start the test',
offset=0x008,
bitSize=32,
bitOffset=0,
base='hex',
mode='RO',
pollInterval=1))
self.add(
pr.Variable(name='initValueReg',
description='Dac value at the start of the test',
offset=0x00C,
bitSize=12,
bitOffset=0,
base='hex',
mode='RW'))
self.add(
pr.Variable(name='endValueReg',
description='Dac value at the end of the test',
offset=0x010,
bitSize=12,
bitOffset=0,
base='hex',
mode='RW'))
self.add(
pr.Variable(
name='delayValueReg',
description=
'Delay values use to settle DAC before and after the test',
offset=0x014,
bitSize=32,
bitOffset=0,
base='hex',
mode='RW'))
self.add(
pr.Variable(name='ssiPrintf',
description='Retrieve data printed on the microblaze',
offset=0x100,
bitSize=1024 * 4,
bitOffset=0,
base='string',
mode='RO'))
def __init__(self, name="iobuff", memBase=None, offset=0, hidden=False, expand=True):
super(self.__class__, self).__init__(name, "Configure IO buffer tristate",
memBase=memBase, offset=offset, hidden=hidden, expand=expand)
"""Add a bit to every buffer"""
self.add(pr.Variable(name="IOBuffer_Disable", offset=offset, bitSize=31, bitOffset=0, base='hex', mode='RW', description=""))
self.add(pr.Variable(name="IOBuffer_testClk_Disable", offset=offset, bitSize=1, bitOffset=0, base='bool', mode='RW', description=""))
self.add(pr.Variable(name="IOBuffer_dacEnL_Disable", offset=offset, bitSize=1, bitOffset=1, base='bool', mode='RW', description=""))
self.add(pr.Variable(name="IOBuffer_term100_Disable", offset=offset, bitSize=1, bitOffset=2, base='bool', mode='RW', description=""))
self.add(pr.Variable(name="IOBuffer_term300_Disable", offset=offset, bitSize=1, bitOffset=3, base='bool', mode='RW', description=""))
self.add(pr.Variable(name="IOBuffer_lvdsTxSel_Disable", offset=offset, bitSize=1, bitOffset=4, base='bool', mode='RW', description=""))
self.add(pr.Variable(name="IOBuffer_acMode_Disable", offset=offset, bitSize=1, bitOffset=5, base='bool', mode='RW', description=""))
self.add(pr.Variable(name="IOBuffer_bitSel_Disable", offset=offset, bitSize=1, bitOffset=6, base='bool', mode='RW', description=""))
#
self.add(pr.Variable(name="IOBuffer_saciClk_Disable", offset=offset, bitSize=1, bitOffset=7, base='bool', mode='RW', description=""))
self.add(pr.Variable(name="IOBuffer_saciCmd_Disable", offset=offset, bitSize=1, bitOffset=8, base='bool', mode='RW', description=""))
self.add(pr.Variable(name="IOBuffer_saciRstL_Disable", offset=offset, bitSize=1, bitOffset=9, base='bool', mode='RW', description=""))
self.add(pr.Variable(name="IOBuffer_saciSelL_0_Disable", offset=offset, bitSize=1, bitOffset=10, base='bool', mode='RW', description=""))
self.add(pr.Variable(name="IOBuffer_saciSelL_1_Disable", offset=offset, bitSize=1, bitOffset=11, base='bool', mode='RW', description=""))
self.add(pr.Variable(name="IOBuffer_saciSelL_2_Disable", offset=offset, bitSize=1, bitOffset=12, base='bool', mode='RW', description=""))
self.add(pr.Variable(name="IOBuffer_saciSelL_3_Disable", offset=offset, bitSize=1, bitOffset=13, base='bool', mode='RW', description=""))
def __init__(self, name="Chess2Array", memBase=None, offset=0, hidden=False, expand=True, enabled=False):
super(self.__class__, self).__init__(name, "CHESS2 Array Interface",
memBase=memBase, offset=offset, hidden=hidden, expand=expand, enabled=enabled)
#################################################################################################
# Using the atlas-chess2/firmware/submodules/surf/protocols/saci/rtl/AxiLiteSaciMaster.vhd module
# AXI_Lite_Address[31:24] = Ignored
# AXI_Lite_Address[23:22] = SACI Chip Select [1:0]
# AXI_Lite_Address[21] = Ignored
# AXI_Lite_Address[20:14] = SACI command [6:0]
# AXI_Lite_Address[13:2] = SACI address [11:0]
# AXI_Lite_Address[1:0] = Ignored
# AXI_Lite_Data[31:0] = SACI data [31:0]
#################################################################################################
# Define the command bit mask
cmd0x0 = (0x0 << 14)
cmd0x1 = (0x1 << 14)
cmd0x2 = (0x2 << 14)
cmd0x3 = (0x3 << 14)
cmd0x4 = (0x4 << 14)
cmd0x5 = (0x5 << 14)
cmd0x8 = (0x8 << 14)
# Define the row and col bit size
rowBitSize = 7
colBitSize = 5
# Create a warning message
warningMessage="""
The values should in principle enforce a functional front-end for CHESS2
and should not be modified without a consultation with the designers as
it could allow too much current to flow in the sensor and damage it.
"""
######################################################
# Define all the non-global registers (A.K.A commands)
######################################################
self.add(pr.Variable(name='StartMatrixConfig',description='START Matrix Configuration',
offset=(cmd0x8), bitSize=32, bitOffset=0, base='bool', mode='WO', hidden=True))
self.add(pr.Variable(name='WritePixel',description='Write Pixel',
offset=(cmd0x5), bitSize=6, bitOffset=0, base='hex', mode='WO', hidden=True))
self.add(pr.Variable(name='EndMatrixConfig',description='END Matrix Configuration',
offset=(cmd0x0), bitSize=32, bitOffset=0, base='bool', mode='RO', hidden=True))
#################################
# Define all the global registers
#################################
self.add(pr.Variable(name='RowPointer',description='Row Pointer',
offset=(cmd0x1|(4*0x1)), bitSize=rowBitSize, bitOffset=0, base='hex', mode='RW'))
self.add(pr.Variable(name='ColPointer', description='Column Pointer',
offset=(cmd0x1|(4*0x3)), bitSize=colBitSize, bitOffset=0, base='hex', mode='RW'))
self.add(pr.Variable(name='VNLogicatt', description=warningMessage,
offset=(cmd0x1|(4*0x5)), bitSize=5, bitOffset=0, base='hex', mode='RW'))
self.add(pr.Variable(name='VNLogicres', description=warningMessage,
offset=(cmd0x1|(4*0x5)), bitSize=2, bitOffset=5, base='hex', mode='RW'))
self.add(pr.Variable(name='VNSFatt', description=warningMessage,
offset=(cmd0x1|(4*0x5)), bitSize=5, bitOffset=7, base='hex', mode='RW'))
self.add(pr.Variable(name='VNSFres', description=warningMessage,
offset=(cmd0x1|(4*0x5)), bitSize=2, bitOffset=12, base='hex', mode='RW'))
self.add(pr.Variable(name='VNatt', description=warningMessage,
offset=(cmd0x1|(4*0x6)), bitSize=5, bitOffset=0, base='hex', mode='RW'))
self.add(pr.Variable(name='VNres', description=warningMessage,
offset=(cmd0x1|(4*0x6)), bitSize=2, bitOffset=5, base='hex', mode='RW'))
self.add(pr.Variable(name='VPFBatt', description=warningMessage,
offset=(cmd0x1|(4*0x6)), bitSize=5, bitOffset=7, base='hex', mode='RW'))
self.add(pr.Variable(name='VPFBres', description=warningMessage,
offset=(cmd0x1|(4*0x6)), bitSize=2, bitOffset=12, base='hex', mode='RW'))
self.add(pr.Variable(name='VPLoadatt', description=warningMessage,
offset=(cmd0x1|(4*0x7)), bitSize=5, bitOffset=0, base='hex', mode='RW'))
self.add(pr.Variable(name='VPLoadres', description=warningMessage,
offset=(cmd0x1|(4*0x7)), bitSize=2, bitOffset=5, base='hex', mode='RW'))
self.add(pr.Variable(name='VPTrimatt', description=warningMessage,
offset=(cmd0x1|(4*0x7)), bitSize=5, bitOffset=7, base='hex', mode='RW'))
self.add(pr.Variable(name='VPTrimres', description=warningMessage,
offset=(cmd0x1|(4*0x7)), bitSize=2, bitOffset=12, base='hex', mode='RW'))
self.add(pr.Variable(name='CLK_bit_sel',description="""
Hit Encoding Clock Selection:
0 - Clock include Matrix load delay
1 - Clock does not includes Matrix Load delay
""",
offset=(cmd0x1|(4*0x8)), bitSize=1, bitOffset=0, base='bool', mode='RW'))
self.add(pr.Variable(name='clk_dly',description='Hit Encoding Delay respect Matrix Clock',
offset=(cmd0x1|(4*0x8)), bitSize=4, bitOffset=1, base='hex', mode='RW'))
self.add(pr.Variable(name='rd_1',description='Reset Distance',
offset=(cmd0x1|(4*0x9)), bitSize=3, bitOffset=0, base='hex', mode='RW'))
self.add(pr.Variable(name='rlt_1',description='Reset Low Time',
offset=(cmd0x1|(4*0x9)), bitSize=3, bitOffset=3, base='hex', mode='RW'))
self.add(pr.Variable(name='wrd_1',description='Reset Write Distance',
offset=(cmd0x1|(4*0x9)), bitSize=3, bitOffset=6, base='hex', mode='RW'))
self.add(pr.Variable(name='DigiMux',description="""
Multiplexer Configuration for digital output monitoring:
0b000 = 0x0 = reset1i
0b001 = 0x1 = writeCLK1i
0b010 = 0x2 = reset2i
0b011 = 0x3 = writeCLK2i
0b000 = 0x4 = wsi
0b001 = 0x5 = CLKi_1_40MHzi
0b010 = 0x6 = CLKi_2_40MHzi
0b011 = 0x7 = gndd!
""",
enum = {0:'reset1i',1:'writeCLK1i',2:'reset2i',3:'writeCLK2i',
4:'wsi',5:'CLKi_1_40MHzi',6:'CLKi_2_40MHzi',7:'gndd'},
offset=(cmd0x1|(4*0x9)), bitSize=3, bitOffset=9, base='enum', mode='RW'))
self.add(pr.Variable(name='wrd_2',description='Reset Write Distance',
offset=(cmd0x1|(4*0xA)), bitSize=3, bitOffset=0, base='hex', mode='RW'))
self.add(pr.Variable(name='rd_2',description='Reset Distance',
offset=(cmd0x1|(4*0xA)), bitSize=3, bitOffset=3, base='hex', mode='RW'))
self.add(pr.Variable(name='rlt_2',description='Reset Low Time',
offset=(cmd0x1|(4*0xA)), bitSize=3, bitOffset=6, base='hex', mode='RW'))
self.add(pr.Variable(name='DelEXEC',description='Exec Delay',
offset=(cmd0x1|(4*0xA)), bitSize=1, bitOffset=9, base='bool', mode='RW'))
self.add(pr.Variable(name='DelCCKreg',description='CCKreg Delay',
offset=(cmd0x1|(4*0xA)), bitSize=1, bitOffset=10, base='bool', mode='RW'))
self.add(pr.Variable(name='LVDS_TX_Current',description='Standard LVDS Current',
offset=(cmd0x1|(4*0xA)), bitSize=1, bitOffset=11, base='bool', mode='RW'))
self.add(pr.Variable(name='LVDS_RX_AC_Mode',description='LVDS Receiver mode',
offset=(cmd0x1|(4*0xA)), bitSize=1, bitOffset=12, base='bool', mode='RW'))
self.add(pr.Variable(name='LVDS_RX_100Ohm',description='DC LVDS Receiver input impedance - 100 Ohm',
offset=(cmd0x1|(4*0xA)), bitSize=1, bitOffset=13, base='bool', mode='RW'))
self.add(pr.Variable(name='LVDS_RX_300Ohm',description='DC LVDS Receiver input impedance - 300 Ohm',
offset=(cmd0x1|(4*0xA)), bitSize=1, bitOffset=14, base='bool', mode='RW'))
self.add(pr.Variable(name='TM',description='Hit Encoding Test Mode',
offset=(cmd0x1|(4*0xA)), bitSize=1, bitOffset=15, base='bool', mode='RW'))
############################
# Add the software variables
############################
self.add(matrix())
