def test_any_does_simulation_correct(self):
r = pyrtl.Register(3, 'r')
r.next <<= r + 1
a, b, c = r[0], r[1], r[2]
o = pyrtl.Output(name='o')
o <<= pyrtl.rtl_any(a, b, c)
self.check_trace('o 01111111\nr 01234567\n')
def prioritized_mux(selects, vals):
"""
Returns the value in the first wire for which its select bit is 1
:param [WireVector] selects: a list of WireVectors signaling whether
a wire should be chosen
:param [WireVector] vals: values to return when the corresponding select
value is 1
:return: WireVector
If none of the items are high, the last val is returned
"""
if len(selects) != len(vals):
raise pyrtl.PyrtlError("Number of select and val signals must match")
if len(vals) == 0:
raise pyrtl.PyrtlError("Must have a signal to mux")
if len(vals) == 1:
return vals[0]
else:
half = len(vals) // 2
return pyrtl.select(pyrtl.rtl_any(*selects[:half]),
truecase=prioritized_mux(selects[:half],
vals[:half]),
falsecase=prioritized_mux(selects[half:],
vals[half:]))
def test_any_does_simulation_correct(self):
r = pyrtl.Register(3, 'r')
r.next <<= r + 1
a, b, c = r[0], r[1], r[2]
o = pyrtl.Output(name='o')
o <<= pyrtl.rtl_any(a, b, c)
self.check_trace('o 01111111\nr 01234567\n')
def prioritized_mux(selects, vals):
"""
Returns the value in the first wire for which its select bit is 1
:param [WireVector] selects: a list of WireVectors signaling whether
a wire should be chosen
:param [WireVector] vals: values to return when the corresponding select
value is 1
:return: WireVector
If none of the items are high, the last val is returned
"""
if len(selects) != len(vals):
raise pyrtl.PyrtlError("Number of select and val signals must match")
if len(vals) == 0:
raise pyrtl.PyrtlError("Must have a signal to mux")
if len(vals) == 1:
return vals[0]
else:
half = len(vals) // 2
return pyrtl.select(pyrtl.rtl_any(*selects[:half]),
truecase=prioritized_mux(selects[:half], vals[:half]),
falsecase=prioritized_mux(selects[half:], vals[half:]))
def test_any_works_with_consts(self):
a = pyrtl.WireVector(name='a', bitwidth=1)
c = pyrtl.WireVector(name='c', bitwidth=1)
r = pyrtl.rtl_any(a, 1, c)
def test_any_only_on_1_bit_vectors(self):
a = pyrtl.WireVector(name='a', bitwidth=3)
b = pyrtl.WireVector(name='b', bitwidth=1)
with self.assertRaises(pyrtl.PyrtlError):
r = pyrtl.rtl_any(a, b)
def vmax(t, *in_list):
combo_list = list(itertools.combinations(in_list, t))
prod_list = [pyrtl.rtl_all(*x) for x in combo_list]
o = pyrtl.rtl_any(*prod_list)
return o
def si(a, b, k, pke, pai, pbi, pae, pbe):
index = rmin(rdelta(pai, a), rdelta(pbi, b))
a0 = pyrtl.rtl_any(rdelta(pae, a), rdelta(pbe, b), rdelta(pke, k))
a1 = pyrtl.rtl_all(rdelta(pae, a), rdelta(pbe, b), pke)
o = mux(index, a0, a1)
return o
def rvcoinc(theshold, sensitivity_window, *in_list):
timer_start = pyrtl.rtl_any(*in_list)
timer = rdelta(sensitivity_window, timer_start)
interwire = rvmax(theshold, *in_list)
o = rinhibit(timer, interwire)
return o
def test_any_works_with_consts(self):
a = pyrtl.WireVector(name='a', bitwidth=1)
c = pyrtl.WireVector(name='c', bitwidth=1)
r = pyrtl.rtl_any(a, 1, c)
def test_any_only_on_1_bit_vectors(self):
a = pyrtl.WireVector(name='a', bitwidth=3)
b = pyrtl.WireVector(name='b', bitwidth=1)
with self.assertRaises(pyrtl.PyrtlError):
r = pyrtl.rtl_any(a, b)
def neuron(delay, threshold, sens_window, exct_inputs, inhib_inputs):
inhibit = pyrtl.rtl_any(*inhib_inputs)
interwire = rvcoinc(threshold, sens_window, *exct_inputs)
signal = rdelta(delay, interwire)
o = rinhibit(inhibit, signal)
return o
