def deploy_and_test(params,
directory,
tests,
board=config.default_board,
part=None,
force_refresh=False,
overwrite_ok=False):
'''
Deploy design to an FPGA and run tests on it there.
The DUT must have an AXI4-LITE interface.
'''
# Make sure this directory is not already deployed.
v_dir = os.path.join(directory, 'vivado')
# Import connection down here so that if it's not available
# we can use other test_utils.
from pyvivado import connection
hwcode = connection.get_projdir_hwcode(v_dir)
assert (hwcode is None)
conn = deploy(
directory=directory,
params=params,
board=board,
part=part,
force_refresh=force_refresh,
overwrite_ok=overwrite_ok,
)
handler = axi.ConnCommandHandler(conn)
for test in tests:
test.set_handler(handler)
test.prepare()
test.check()
# Sleep for 10 seconds so that we can kill monitor
time.sleep(10)
# Destroy monitoring process
connection.kill_free_monitors(v_dir)
def deploy_and_test(
params, directory, tests, board=config.default_board,
part=None, force_refresh=False, overwrite_ok=False):
'''
Deploy design to an FPGA and run tests on it there.
The DUT must have an AXI4-LITE interface.
'''
# Make sure this directory is not already deployed.
v_dir = os.path.join(directory, 'vivado')
# Import connection down here so that if it's not available
# we can use other test_utils.
from pyvivado import connection
hwcode = connection.get_projdir_hwcode(v_dir)
assert(hwcode is None)
conn = deploy(
directory=directory, params=params,
board=board,
part=part,
force_refresh=force_refresh,
overwrite_ok=overwrite_ok,
)
handler = axi.ConnCommandHandler(conn)
for test in tests:
test.set_handler(handler)
test.prepare()
test.check()
# Sleep for 10 seconds so that we can kill monitor
time.sleep(10)
# Destroy monitoring process
connection.kill_free_monitors(v_dir)
def get_monitors_hwcode(self, monitor_task):
'''
Get the hardware code for the FPGA that this project has been deployed to.
'''
max_waits = 120
n_waits = 0
hwcode = None
while (hwcode is None) and (n_waits < max_waits) and (not monitor_task.is_finished()):
hwcode = connection.get_projdir_hwcode(self.directory)
n_waits += 1
time.sleep(1)
# If the task is finished something must have gone wrong
# so log it's messages.
if monitor_task.is_finished():
monitor_task.log_messages(monitor_task.get_messages())
deploy_errors = monitor_task.get_errors()
logger.debug('Waited {}s to see deployment'.format(n_waits))
if (len(deploy_errors) != 0):
raise Exception('Got send_to_fpga_and_monitor errors.')
if hwcode is None:
raise Exception('Failed to deploy project')
return hwcode
def get_monitors_hwcode(self, monitor_task):
'''
Get the hardware code for the FPGA that this project has been deployed to.
'''
max_waits = 120
n_waits = 0
hwcode = None
while (hwcode is None) and (n_waits < max_waits) and (not monitor_task.is_finished()):
hwcode = connection.get_projdir_hwcode(self.directory)
n_waits += 1
time.sleep(1)
# If the task is finished something must have gone wrong
# so log it's messages.
if monitor_task.is_finished():
monitor_task.log_messages(monitor_task.get_messages())
deploy_errors = monitor_task.get_errors()
logger.debug('Waited {}s to see deployment'.format(n_waits))
if (len(deploy_errors) != 0):
raise Exception('Got send_to_fpga_and_monitor errors.')
if hwcode is None:
raise Exception('Failed to deploy project')
return hwcode